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W90N745cd/W90N745cdg 32-bit arm7tdmi-based mcu W90N745 16/32-bit arm microcontroller product data sheet free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - i - revision a2 revision history revision date comments a 2006/06/23 draft a1 2006/08/30 add electrical specification a2 2006/09/22 delete chapter 6: block diagram free datasheet http:///
W90N745cd/W90N745cdg - ii - table of contents- 1. general des cription ......................................................................................................... 1 2. features ....................................................................................................................... .......... 2 3. pin diag ram .................................................................................................................... ........ 7 4. pin assign ment ................................................................................................................. .... 8 5. pin descri ption................................................................................................................ ... 13 6. functional d escription ................................................................................................. 24 6.1 arm7tdmi cpu co re ............................................................................................... 24 6.2 system manager ........................................................................................................... 25 6.2.1 overvi ew ....................................................................................................................... . 25 6.2.2 system memo ry map...................................................................................................... 25 6.2.3 address bus generat ion ................................................................................................ 28 6.2.4 data bus connection with external memory .................................................................. 28 6.2.5 bus arbitr ation................................................................................................................ 37 6.2.6 power m anagement ....................................................................................................... 38 6.2.7 power-on setti ng ........................................................................................................... 41 6.2.8 system manager contro l register s map ........................................................................ 41 6.3 external bus interface .................................................................................................. 56 6.3.1 ebi over view.................................................................................................................. 56 6.3.2 sdram cont rolle r .......................................................................................................... 56 6.3.3 ebi control r egisters map ............................................................................................. 60 6.4 cache cont roller........................................................................................................... 79 6.4.1 on-chip ram ................................................................................................................. 79 6.4.2 non-cacheabl e ar ea ...................................................................................................... 79 6.4.3 instructi on cac he............................................................................................................ 80 6.4.4 data ca che .................................................................................................................... 82 6.4.5 write bu ffer ................................................................................................................... . 84 6.4.6 cache control r egisters map......................................................................................... 84 6.5 ethernet mac controller............................................................................................... 92 6.5.1 emc functional descrip tion ........................................................................................... 93 6.5.2 emc register mappi ng ................................................................................................ 103 6.6 gdma cont roller ........................................................................................................ 158 6.6.1 gdma functional descrip tion ...................................................................................... 158 6.6.2 gdma regist er map .................................................................................................... 159 6.7 usb host c ontroller ................................................................................................... 168 6.7.1 usb host functi onal descr ipti on ................................................................................. 168 6.7.2 usb host controlle r register s map ............................................................................. 169 6.8 usb device controller................................................................................................ 192 6.8.1 usb endpoi nts ............................................................................................................. 192 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - iii - revision a2 6.8.2 standard device reques t............................................................................................. 192 6.8.3 usb device regist er descr ipti on ................................................................................. 192 6.9 audio cont roller .......................................................................................................... 231 6.9.1 i2s inte rface.................................................................................................................. 231 6.9.2 ac97 inte rface ............................................................................................................. 232 6.9.3 audio controller register map...................................................................................... 235 6.10 universal asynchronous receiv er/transmitter contro ller ......................................... 254 6.10.1 uart0........................................................................................................................ 256 6.10.2 uart1........................................................................................................................ 256 6.10.3 uart2........................................................................................................................ 258 6.10.4 uart3........................................................................................................................ 260 6.10.5 general uart contro ller ........................................................................................... 261 6.10.6 high speed uart contro ller ...................................................................................... 274 6.11 timer/watchdog contro ller......................................................................................... 288 6.11.1 general timer contro ller ............................................................................................ 288 6.11.2 watchdog ti mer ......................................................................................................... 288 6.11.3 timer control r egisters map...................................................................................... 288 6.12 advanced interrupt contro ller..................................................................................... 297 6.12.1 interrupt source s ........................................................................................................ 298 6.12.2 aic regist ers ma p ..................................................................................................... 301 6.13 general-purpose input/o utput ................................................................................... 314 6.13.1 gpio register descrip tion ......................................................................................... 316 6.13.2 gpio register descrip tion ......................................................................................... 317 6.14 i 2 c interf ace ................................................................................................................ 338 6.14.1 i 2 c prot ocol ................................................................................................................ 339 6.14.2 i 2 c serial interface c ontrol regist ers map ................................................................. 342 6.15 universal serial interface............................................................................................ 349 6.15.1 usi timing diagr am ................................................................................................... 350 6.15.2 usi regist ers ma p ..................................................................................................... 351 6.16 pwm ........................................................................................................................... 358 6.16.1 pwm double buffering and reload auto matica lly...................................................... 359 6.16.2 modulate duty ratio ................................................................................................... 359 6.16.3 dead zone g enerat or................................................................................................. 360 6.16.4 pwm timer star t proc edure ...................................................................................... 360 6.16.5 pwm timer st op proc edure....................................................................................... 360 6.16.6 pwm regist er map .................................................................................................... 361 6.17 keypad inte rface......................................................................................................... 371 6.17.1 keypad interface register map .................................................................................. 372 6.17.2 register de scripti on ................................................................................................... 373 free datasheet http:///
W90N745cd/W90N745cdg - iv - 6.18 ps2 host interf ace cont roller ..................................................................................... 380 6.18.1 ps2 host controller inte rface regist er map............................................................... 381 6.18.2 register de scripti on ................................................................................................... 382 7. electrical spec ifications........................................................................................... 386 7.1 absolute maxi mum ra tings ........................................................................................ 386 7.2 dc specific ations ....................................................................................................... 386 7.2.1 digital dc char acterist ics............................................................................................. 386 7.2.2 usb transceiver dc characteri stics............................................................................ 388 7.3 ac specif icati ons........................................................................................................ 389 7.3.1 ebi/sdram interface ac characte ristics .................................................................... 389 7.3.2 ebi/(rom/sram/external i/o) ac charac teristics ...................................................... 390 7.3.3 usb transceiver ac characteri stics............................................................................ 391 7.3.4 emc rmii ac char acterist ics ...................................................................................... 391 7.3.5 ac97/i2s interface ac characte ristics......................................................................... 393 7.3.6 i 2 c interface ac c haracteri stics ................................................................................... 395 7.3.7 usi interface ac characteri stics .................................................................................. 396 7.3.8 ps2 interface ac characteri stics ................................................................................. 397 8. ordering in formation .................................................................................................. 399 9. package specif ications................................................................................................ 400 10. appendix a: W90N745 regist ers mapping table .................................................... 401 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 1 - revision a2 1. general description the W90N745 is built around an outstanding cpu core , the 16/32 arm7tdmi risc processor which designed by advanced risc machines, ltd. it offers 4k-byte i-cache/sram and 4k-byte d- cache/sram, is a low power, general purpose integrat ed circuits. its simple, elegant, and fully static design is particularly suitable for cost sensitive and power s ensitive applications. one 100/10 mbit mac of ethernet controller is built-in to reduce total system cost. the W90N745 also provides one usb 1.1 host c ontroller, one usb 1.1 device controller, one ac97/i2s controller, one 2-channel gdma, four independent uarts, one watchdog timer, two 24-bit timers with 8-bit pre-scale, up to 31 progra mmable i/o ports, ps2 keyboard controller and an advanced interrupt controller. the external bus in terface (ebi) controller provides for sdram, rom/sram, flash memory and i/o devices. the syst em manager includes an internal 32-bit system bus arbiter and a pll clock controller. with a wide range of serial communication and et hernet interfaces, the W90N745 is suitable for communication gateways as well as m any other general purpose applications. free datasheet http:///
W90N745cd/W90N745cdg - 2 - 2. features architecture ? fully 16/32-bit risc architecture ? little/big-endian mode supported ? efficient and powerful arm7tdmi core ? cost-effective jtag-based debug solution external bus interface ? 8/16-bit external bus support for rom/sr am, flash memory, sdram and external i/os ? support for sdram ? programmable access cycle (0-7 wait cycle) ? four-word depth write buffer for sdram write data ? cost-effective memory-to-peripheral dma interface instruction and data cache ? two-way, set-associative, 4k -byte i-cache and 4k-byte d-cache ? support for lru (least recently used) protocol ? cache can be configured as internal sram ? support cache lock function ethernet mac controller ? dma engine with burst mode ? mac tx/rx buffers (256 bytes tx, 256 bytes rx) ? data alignment logic ? endian translation ? 100/10 mbit per second operation ? full compliance with ieee standard 802.3 ? rmii interface only ? station management signaling ? on-chip cam (up to 16 destination addresses) ? full-duplex mode with pause feature ? long/short packet modes ? pad generation free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 3 - revision a2 dma controller ? 2-channel general dma for memory-to-memory data transfers without cpu intervention ? initialed by a software or external dma request ? increments or decrements a source or destinati on address in 8-bit, 16-bit or 32-bit data transfers ? 4-data burst mode uart ? four uart (serial i/o) blocks with interrupt-based operation ? support for 5-bit, 6-bit, 7-bit or 8- bit serial data transmit and receive ? programmable baud rates ? 1, ? or 2 stop bits ? odd or even parity ? break generation and detection ? parity, overrun and framing error detection ? x16 clock mode ? uart1 supports bluetooth, and uart2 supports irda1.0 sir timers ? two programmable 24-bit timers with 8-bit pre-scaler ? one programmable 20 bit with selectable additional 8-bit prescaler watchdog timer ? one-shot mode, periodical mode or toggle mode operation programmable i/os ? 31 programmable i/o ports ? pins individually configurable to input, output or i/o mode for dedicated signals ? i/o ports are configurable for multiple functions advanced interrupt controller ? 24 interrupt sources, including 4 external interrupt sources ? programmable normal or fast interrupt mode (irq, fiq) ? programmable as either edge-triggered or level- sensitive for 4 external interrupt sources ? programmable as either low-active or hi gh-active for 4 external interrupt sources ? priority methodology is encoded to allow for interrupt daisy-chaining ? automatically mask out the lower priority interrupt during interrupt nesting free datasheet http:///
W90N745cd/W90N745cdg - 4 - usb host controller ? usb 1.1 compliant ? compatible with open hci 1.0 specification ? supports low-speed and full speed devices ? build-in dma for real time data transfer ? two on-chip usb transceivers with one opt ionally shared with usb device controller usb device controller ? usb 1.1 compliant ? support four usb endpoints including one contro l endpoint and 3 configurable endpoints for rich usb functions two plls ? the external clock can be multiplied by on-ch ip pll to provide high frequency system clock ? the input frequency range is 3- 30mhz; 15mhz is preferred. ? one pll for both cpu and usb host/device controller ? one pll for audio i2s 12.288/16.934mhz clock source ? programmable clock frequency 4-channel pwm ? four 16-bit timers with pwm ? two 8-bit pre-scalers & two 4-bit dividers ? programmable duty control of output waveform (pwm) ? auto reload mode or one-shot pulse mode ? dead-zone generator i 2 c master ? 2-channel i 2 c ? compatible with philips i 2 c standard, support master mode only ? support multi master operation ? clock stretching and wait state generation ? provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer ? software programmable acknowledge bit ? arbitration lost interrupt, with automatic transfer cancellation ? start/stop/repeated st art/acknowledge generation ? start/stop/repeated start detection ? bus busy detection free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 5 - revision a2 ? supports 7 bit addressing mode ? software mode i 2 c universal serial interface (usi) ? 1-channel usi ? support usi (microwire/spi) master mode ? full duplex synchronous serial data transfer ? variable length of transfer word up to 32 bits ? provide burst mode operation, transmit/receive can be executed up to four times in one transfer ? msb or lsb first data transfer ? rx and tx on both rising or falli ng edge of serial clock independently ? two slave/device select lines ? fully static synchronous design with one clock domain 2-channel ac97/i2s audio codec host interface ? ahb master port and an ahb slave por t are offered in audio controller. ? always 8-beat incrementing burst ? always bus lock when 8-beat incrementing burst ? when reach middle and end address of destinati on address, a dma_irq is requested to cpu automatically keypad scan interface ? scan up to 16 rows by 8 columns with an exter nal 4 to 16 decoder and 4x8 array without auxiliary component ? programmable debounce time ? one or two keys scan with interr upt and three keys reset function. ? wakeup cpu from idel/power down mode ps2 host interface ? apb slave consisted of ps2 protocol. ? connect ibm keyboard or bar-code reader through ps2 interface. ? provide hardware scan code to ascii translation free datasheet http:///
W90N745cd/W90N745cdg - 6 - power management ? programmable clock enables for individual peripheral ? idle mode to halt arm core and keep peripheral working ? power-down mode to stop all clocks included external crystal oscillator. ? exit idle by all interrupts y exit power-down by keypad,u sb device and external interrupts operation voltage range ? 3.0 ~ 3.6 v for io buffer ? 1.62 ~ 1.98 v for core logic operation temperature range ? tbd operating frequency ? up to 80 mhz package type ? 128-pin lqfp free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 7 - revision a2 3. pin diagram figure 3.1 pin diagram free datasheet http:///
W90N745cd/W90N745cdg - 8 - 4. pin assignment table 4.1 W90N745 pins assignment pin name 128-pin lqfp clock & reset ( 3 pins ) extal (15m) 40 xtal (15m) 41 nreset 25 jtag interface ( 5 pins ) tms 33 tdi 34 tdo 35 tck 36 ntrst 37 external bus interface ( 53 pins ) a [20:0] 89-86,84-82,80-77,75-71,69-65 d [15:0] 110-111,113-116,118-122,124-128 nwbe [1;0] / sdqm [1:0] 108,107 nscs [1:0] 100,99 nsras 101 nscas 102 mcke 98 nswe 106 mclk 104 nwait / gpio [30] / nirq [3] 96 nbtcs 97 necs [3:0] 90,92-94 noe 95 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 9 - revision a2 table 4.1 W90N745 pins assignment, continued pin name 128-pin lqfp ethernet interface ( 10 pins ) phy_mdc / gpio [29] / kprow [1] 64 phy_mdio / gpio [28] / kprow [0] 63 phy_txd [1:0] / gpio [27:26] / kpcol [7:6] 62,60 phy_txen / gpio [25] / kpcol [5] 59 phy_refclk / gpio [24] / kpcol [4] 58 phy_rxd [1:0] / gpio [23:22] / kpcol [3:2] 57,55 phy_crsdv / gpio [21] / kpcol [1] 54 phy_rxerr / gpio [20] / kpcol [0] 53 ac97/i 2 s/pwm/uart3 ( 5 pins ) ac97_nreset / i2s_mclk / gpio [0] / nirq [2] / usb_pwren 44 free datasheet http:///
W90N745cd/W90N745cdg - 10 - table 4.1 W90N745 pins assignment, continued pin name 128-pin lqfp ac97/i 2 s/pwm/uart3 ( 5 pins ) ac97_datai / i2s_datai / pwm [0] / dtr3 / gpio [1] 45 ac97_datao / i2s_datao / pwm [1] / dsr3 / gpio [2] 46 ac97_sync / i2s_lrclk / pwm [2] / txd3 / gpio [3] 47 ac97_bitclk / i2s_bitclk / pwm [3] / rxd3 gpio [4] 48 usb interface ( 4 pins ) dp0 7 dn 0 6 dp1 2 dn1 3 miscellaneous ( 7 pins ) nirq [1] / gpio [17] / usb_ovrcur 32 nirq [0] / gpio [16] 31 nwdog / gpio [15] / usb_pwren 38 test 26 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 11 - revision a2 table 4.1 W90N745 pins assignment, continued pin name 128-pin lqfp i 2 c/usi(spi/mw) ( 4 pins ) scl0 / sfrm / timer0 / gpio [11] 17 sda0 / ssptxd / timer1 / gpio [12] 18 scl1 / sclk / gpio [13] / kprow [3] 19 sda1 / ssprxd / gpio [14] / kprow [2] 20 uart0/uart1/uart2/ps2 ( 6 pins ) txd0 / gpio [5] 10 rxd0 / gpio [6] 11 txd1 / gpio [7] 12 rxd1 / gpio [8] 13 cts1 / txd2(irda) / ps2_clk / gpio [9] 14 rts1 / rxd2(irda) / ps2_data / gpio [10] 15 free datasheet http:///
W90N745cd/W90N745cdg - 12 - table 4.1 W90N745 pins assignment, continued pin name 128-pin lqfp xdma ( 2 pins ) nxdreq / gpio [19] / 51 nxdack / gpio [18] / 52 power/ground ( 36 pins ) vdd18 21,43,49,85,112 vss18 22,50,81,109 vdd33 9,23,42,61,76,103,117 vss33 16,24,39,56,70,91,105,123 usbvdd 1,8 usbvss 4,5 pllvdd18 27,30 pllvss18 28,29 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 13 - revision a2 5. pin description table 5.1 W90N745 pins description pin name io type description clock & reset extal (15m) i 15mhz exter nal clock / crystal input xtal (15m) o 15mhz crystal output nreset is system reset, active-low jtag interface tms ius jtag test mode select, internal pull-up with 70k ohm tdi ius jtag test data in, internal pull-up with 70k ohm tdo o jtag test data out tck ids jtag test clock, internal pull-down with 58k ohm ntrst ius jtag reset, active-low, internal pull-up with 70k ohm external bus interface a [20:18] o address bus (msb) of external memory and io devices. a [17:0] ios address bus of external memory and io devices. d [15:0] ios data bus (lsb) of external memory and io device. nwbe [1:0] / sdqm [1:0] ios write byte enable for specific device (necs [1:0]). data bus mask signal for sdra m (nscs [1:0]), active-low. nscs [1:0] o sdram chip select fo r two external banks, active-low. nsras o row address strobe for sdram, active-low. nscas o column address strobe for sdram, active-low. mcke o sdram clock enable, active-high nswe o sdram write enable, active-low mclk o system master clock out, sdram clock, output with slew-rate control nwait / gpio[30] / nirq3 ius external wait, active-low. this pin i ndicates that the external devices need more active cycle during access operation. general programmable in/out port gpio[ 30]. if memory and io devices in ebi do not need wait request, it can be c onfigured as gpio[30] or nirq3. nbtcs o rom/flash chip select, active-low. necs [3:0] io external i/o chip select, active-low. noe o rom/flash, external memo ry output enable, active-low. free datasheet http:///
W90N745cd/W90N745cdg - 14 - table 5.1 W90N745 pins description, continued pin name io type description ethernet interface phy_mdc / gpio [29] / kprow [1] iou rmii management data clock for ethernet. it is the reference clock of mdio. each mdio data will be latched at the rising edge of mdc clock. general programmable in/out port [29] keypad row[1] scan output. phy_mdio / gpio [28] / kprow [0] io rmii management data i/o for ethernet. it is used to transfer rmii control and status information between phy and mac. general programmable in/out port [28] keypad row[0] scan output. phy_txd [1:0] / gpio [27:26] / kpcol [7:6] iou 2-bit transmit data bus for ethernet. general programmable in/out port [27:26] keypad column input [7:6], active low phy_txen / gpio [25] / kpcol [5] iou phy_txen shall be asserted synchronously with the first 2-bit of the preamble and shall remain asserted while all di-b its to be transmitted are presented. of course, it is synchronized with phy_refclk. general programmable in/out port [25] keypad column input [5], active low phy_refclk / gpio [24] / kpcol [4] ios reference clock. the clock shall be 50mhz +/- 50 ppm with minimum 35% duty cycle at high or low state. general programmable in/out port [24] keypad column input [4], active low phy_rxd [1:0] / gpio [23:22] / kpcol [3:2] ios 2-bit receive data bus for ethernet. general programmable in/out port [23:22] keypad column input [3:2], active low phy_crsdv / gpio [21] / kpcol [1] ios carrier sense / receive data valid for ethernet. the phy_crsdv shall be asserted by phy when the receive medium is non-idle. loss of carrier shall result in the de-assertion of phy_ crsdv synchronous to the cycle of phy_refclk, and only on 2-bit receive data boundaries. general programmable in/out port [21] keypad column input [1], active low phy_rxerr / gpio [20] / kpcol [0] ios receive data error for ethernet. it indi cates a data error detected by phy.the assertion should be lasted for longer than a period of phy_refclk. when phy_rxerr is asserted, the mac will report a crc error. general programmable in/out port [20] keypad column input [0], active low free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 15 - revision a2 table 5.1 W90N745 pins description, continued pin name io type description ac97/i 2 s/pwm/uart3 ac97_nreset / i 2 s_mclk / gpio [0] / nirq [2] / usb_pwren iou ac97 codec host interface reset output. i 2 s codec host interface system clock output. general purpose in/out port [0] external interrupt request. usb host power enable output ac97_datai / i 2 s_datai / pwm [0] / dtr3 / gpio [1] iou ac97 codec host interface data input. i 2 s codec host interface data input. pwm channel 0 output. data terminal ready for uart3. general purpose in /out port [1] ac97_datao / i 2 s_datao / pwm [1] / dsr3 / gpio [2] iou ac97 codec host interface data output. i 2 s codec host interface data output. pwm channel 1 output. data set ready for uart3. general purpose in/out port [2] ac97_sync / i 2 s_lrclk / pwm [2] / txd3 / gpio [3] iou ac97 codec host interface synchronous pulse output. i 2 s codec host interface left/ right channel select clock. pwm channel 2 output. transmit data for uart3. general purpose in/out port [3] ac97_bitclk / i 2 s_bitclk / pwm [3] / rxd3 / gpio [4] ios ac97 codec host interface bit clock input. i 2 s codec host interface bit clock. pwm channel 3 output. receive data for uart3. general purpose in/out port [4]. usb interface dp0 io differential positive usb io signal dn0 io differential negative usb io signal dp1 io differential positive usb io signal dn1 io differential negative usb io signal miscellaneous nirq [1:0] / gpio [17:16] / usb_ovrcur iou external interrupt request general purpose i/o nirq1 is used as usb host ov er-current detection input nwdog / gpio [15] / usb_pwren iou watchdog timer timeout flag and keypad 3-keys reset output, active low general purpose in/output usb host power switch enable output test ids this test pin must be short to ground or left unconnected free datasheet http:///
W90N745cd/W90N745cdg - 16 - table 5.1 W90N745 pins description, continued pin name io type description i 2 c/usi scl0 / sfrm / timer0 / gpio [11] iou i 2 c serial clock line 0. usi serial frame. timer0 time out output. general purpose in/out port [11]. sda0 / ssptxd / timer1 / gpio [12] iou i 2 c serial data line 0 usi serial transmit data timer1 time out output general purpose in/out port [12] scl1 / sclk / gpio [13] / kprow [3] iou i 2 c serial clock line 1 usi serial clock general purpose in/out port [13] keypad row scan output [3] sda1 / ssprxd / gpio [14] / kprow [2] idu i 2 c serial data line 1 usi serial receive data general purpose in/out port [14] keypad scan output [2] uart0/uart1/uart2 txd0 / gpio [5] iou uart0 transmit data. general purpose in/out [5] rxd0 / gpio [6] iou uart0 receive data. general purpose in/out [6] txd1 / gpio [7] iou uart1 transmit data. general purpose in/out [7] rxd1 / gpio [8] iou uart1 receive data. general purpose in/out [8] cts1/ txd2(irda) / ps2_clk / gpio [9] iou uart1 clear to send for bluetooth application uart2 transmit data supporting sir irda. ps2 interface clock input/output general purpose in/out [9] rts1/ rxd2(irda) / ps2_data / gpio [10] iou uart1 request to send for bluetooth application uart2 receive data supporting sir irda. ps2 interface bi-directional data line. general purpose in/out [10] xdma nxdreq / gpio [19] / io external dma request. general purpose in/out [19] nxdack / gpio [18] / io external dma acknowledgement. general purpose in/out [18] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 17 - revision a2 table 5.1 W90N745 pins description, continued pin name io type description power/ground vdd18 p core logic power (1.8v) vss18 g core logic ground (0v) vdd33 p io buffer power (3.3v) vss33 g io buffer ground (0v) usbvdd p usb power (3.3v) usbvss g usb ground (0v) dvdd18 p pll digital power (1.8v) dvss18 g pll digital ground (0v) avdd18 p pll analog power (1.8v) avss18 g pll analog ground (0v) free datasheet http:///
W90N745cd/W90N745cdg - 18 - table 5.2 W90N745 128-pin lqfp multi-function list pin no. default function0 function1 function2 function3 usb1.1 host/device interface 1 usbvdd usbvdd - - - 2 dp1 dp1 - - - 3 dn1 dn1 - - - 4 usbvss usbvss - - - 5 usbvss usbvss - - - 6 dn0 dn0 - - - 7 dp0 dp0 - - - 8 usbvdd usbvdd - - - 9 vdd33 vdd33 - - - uart[2:0]/ps2 interface 10 gpio[5] gpio[5] uart_txd0 - - 11 gpio[6] gpio[6] uart_rxd0 - - 12 gpio[7] gpio[7] uart_txd1 - - 13 gpio[8] gpio[8] uart_rxd1 - - 14 gpio[9] gpio[9] uart_txd2 uart_cts1 ps2_clk 15 gpio[10] gpio[10] uart_rxd2 uart_rts1 ps2_data 16 vss33 vss33 - - - i 2 c/usi interface 17 gpio[11] gpio[11] i 2 c_scl0 ssp_fram timer0 18 gpio[12] gpio[12] i 2 c_sda0 ssp_txd timer1 19 gpio[13] gpio[13] i 2 c_scl1 ssp_sclk kpi_row[3] 20 gpio[14] gpio[14] i 2 c_sda1 ssp_rxd kpi_row[2] 21 vdd18 vdd18 - - - 22 vss18 vss18 - - - 23 vdd33 vdd33 - - - 24 vss33 vss33 - - - system reset & test 25 nreset nreset - - - 26 test test - - - free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 19 - revision a2 table 5.2 W90N745 128-pin lqfp multi-function list, continued pll power/ground 27 pll_vdd18 pll_vdd18 - - - 28 pll_vss18 pll_vss18 - - - 29 pll_vss18 pll_vss18 - - - 30 pll_vdd18 pll_vdd18 - - - external irq[1:0]/usb over current 31 gpio[16] gpio[16] nirq [0] - - 32 gpio[17] gpio[17] nirq [1] usb_ovrcur - jtag interface 33 tms tms - - - 34 tdi tdi - - - 35 tdo tdo - - - 36 tck tck - - - 37 ntrst ntrst - - - watchdog/usb power enable 38 gpio[15] gpio[15] nwdog usb_pwren - 39 vss33 vss33 - - - system clock 40 extal(15m) extal(15m) - - - 41 xtal(15m) xtal(15m) - - - 42 vdd33 vdd33 - - - 43 vdd18 vdd18 - - - free datasheet http:///
W90N745cd/W90N745cdg - 20 - table 5.2 W90N745 128-pin lqfp multi-function list, continued pin no. default function0 function1 function2 function3 ac97/i 2 s/pwm/uart3 interface 44 gpio[0] gpio[0] ac97_nreset or i 2 smclk nirq [2] usb_pwren 45 gpio[1] gpio[1] ac97_datai or i 2 sdatai pwm0 uart_dtr3 46 gpio[2] gpio[2] ac97_datao or i 2 sdatao pwm1 uart_dsr3 47 gpio[3] gpio[3] ac97_sync or i 2 slrclk pwm2 uart_txd3 48 gpio[4] gpio[4] ac97_bitclk or i 2 sbitclk pwm3 uart_rxd3 49 vdd18 vdd18 - - - 50 vss18 vss18 - - - xdmareq 51 gpio[19] gpio[19] nxdreq - - 52 gpio[18] gpio[18] nxdack - - ethernet rmii/keypad interface 53 gpio[20] gpio[20] phy_rxerr kpi_col[0] - 54 gpio[21] gpio[21] phy_crsdv kpi_col[1] - 55 gpio[22] gpio[22] phy_rxd[0] kpi_col[2] - 56 vss33 vss33 - - - 57 gpio[23] gpio[23] phy_rxd[1] kpi_col[3] - 58 gpio[24] gpio[24] phy_refclk kpi_col[4] - 59 gpio[25] gpio[25] phy_txen kpi_col[5] - 60 gpio[26] gpio[26] phy_txd[0] kpi_col[6] - 61 vdd33 vdd33 - - - 62 gpio[27] gpio[27] phy_txd[1] kpi_col[7] - 63 gpio[28] gpio[28] phy_mdio kpi_row[0] 64 gpio[29] gpio[29] phy_mdc kpi_row[1] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 21 - revision a2 table 5.2 W90N745 128-pin lqfp multi-function list, continued pin no. default function0 function1 function2 function3 memory address/data/control 65 a[0] a[0] - - - 66 a[1] a[1] - - - 67 a[2] a[2] - - - 68 a[3] a[3] - - - 69 a[4] a[4] - - - 70 vss33 vss33 - - - 71 a[5] a[5] - - - 72 a[6] a[6] - - - 73 a[7] a[7] - - - 74 a[8] a[8] - - - 75 a[9] a[9] - - - 76 vdd33 vdd33 - - - 77 a[10] a[10] - - - 78 a[11] a[11] - - - 79 a[12] a[12] - - - 80 a[13] a[13] - - - 81 vss18 vss18 - - - 82 a[14] a[14] - - - 83 a[15] a[15] - - - 84 a[16] a[16] - - - 85 vdd18 vdd18 - - - 86 a[17] a[17] - - - 87 a[18] a[18] - - - 88 a[19] a[19] - - - 89 a[20] a[20] - - - 90 necs[3] necs[3] - - - 91 vss33 vss33 - - - free datasheet http:///
W90N745cd/W90N745cdg - 22 - table 5.2 W90N745 128-pin lqfp multi-function list, continued pin no. default function0 function1 function2 function3 memory address/data/control 92 necs[2] necs[2] - - - 93 necs[1] necs[1] - - - 94 necs[0] necs[0] - - - 95 noe noe - - - 96 nwait gpio[30] nwait nirq [3] - 97 nbtcs nbtcs - - - 98 mcke mcke - - - 99 nscs[0] nscs[0] - - - 100 nscs[1] nscs[1] - - - 101 nsras nsras - - - 102 nscas nscas - - - 103 vdd33 vdd33 - - - 104 mclk mclk - - - 105 vss33 vss33 - - - 106 nswe nswe - - - 107 nwbe/sdqm[0] nwbe or sdqm[0] 108 nwbe/sdqm[1] nwbe or sdqm[1] 109 vss18 vss18 - - - 110 d[15] d[15] - - - 111 d[14] d[14] - - - 112 vdd18 vdd18 - - - 113 d[13] d[13] - - - 114 d[12] d[12] - - - 115 d[11] d[11] - - - 116 d[10] d[10] - - - 117 vdd33 vdd33 - - - 118 d[9] d[9] - - - 119 d[8] d[8] - - - 120 d[7] d[7] - - - free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 23 - revision a2 table 5.2 W90N745 128-pin lqfp multi-function list, continued pin no. default function0 function1 function2 function3 memory address/data/control 121 d[6] d[6] - - - 122 d[5] d[5] - - - 123 vss33 vss33 - - - 124 d[4] d[4] - - - 125 d[3] d[3] - - - 126 d[2] d[2] - - - 127 d[1] d[1] - - - 128 d[0] d[0] - - - free datasheet http:///
W90N745cd/W90N745cdg - 24 - 6. functional description 6.1 arm7tdmi cpu core the arm7tdmi cpu core is a member of the advanced risc machines (arm) family of general- purpose 32-bit microprocessors, which offer high per formance for very low power consumption. the architecture is based on reduced instruction set com puter (risc) principles, and the instruction set and related decode mechanism are much simpler than thos e of micro-programmed complex instruction set computers. pipelining is employed so that all par ts of the processing and me mory systems can operate continuously. the high instruction throughput and impressi ve real-time interrupt response are the major benefits. the arm7tdmi cpu core has two instruction sets: (1) the standard 32-bit arm set (2) a 16-bit thumb set the thumb set?s 16-bit instruction length allows it to approach twice the density of standard arm core while retaining most of the arm?s performance advant age over a traditional 16-bit processor using 16-bit registers. thumb instructions oper ate with the standard arm register configuration, allowing excellent interoperability between arm and thumb states. each 16-bit thumb instruction has a corresponding 32-bit arm instruction with the same effect on the processor model. arm7tdmi cpu core has 31 x 32-bit registers. at any one time, 16 sets are visible; the other registers are used to speed up exception processing. all the r egister specified in arm instructions can address any of the 16 registers. the cpu al so supports 5 types of exception, such as two levels of interrupt, memory aborts, attempted execution of an undefined instruction and software interrupts. address register address incrementer barrel shifter register bank (31 x 32-bit registers) (6 status registers) 32 x8 multiplier 32-bit alu writer data register instruction pipeline read data register thumb instruction decoder instruction decoder control logic scan control b bus a bus alu bus pc bus incrementer bus a[31:0] d[31:0] figure 6.1.1 arm7tdmi cpu core block diagram free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 25 - revision a2 6.2 system manager 6.2.1 overview the W90N745 system manager has the following functions. y system memory map y data bus connection with external memory y product identifier register y bus arbitration y pll module y clock select and power saving control register y power-on setting 6.2.2 system memory map W90N745 provides 2g bytes cacheable address spac e and the other 2g bytes are non-cacheable. the on-chip peripherals bank is on 1m bytes top of the space (0xfff0_0000 ? 0xffff_ffff) and the on- chip ram bank?s start address is 0xffe0.0000, t he other banks can be located anywhere (cacheable space:0x0000_0000~0x7fdf_ffff if cache on; non-cacheable space: 0x8000_0000~0xffdf_ffff). the size and location of each bank is determined by t he register settings for ?current bank base address pointer? and ?current bank size?. please note that when setting the bank control registers, the address boundaries of consecutive ban ks must not overlap. except on-chip peripherals and on-chi p ram, the start address of each memory bank is not fixed. you can use bank control registers to assign a specific bank start address by setting the bank?s base pointer (13 bits). the address resolution is 256k bytes. t he bank?s start address is defined as ?base pointer << 18? and the bank?s size is ?current bank size?. in the event of an access requested to an address outside any programmed bank size, an abort signal is generated. the maximum accessible memory size of each external io bank is 4m bytes (by word format), and 64m bytes on each sdram bank. free datasheet http:///
W90N745cd/W90N745cdg - 26 - rom/flash 256 kb - 4mb sdram bank 0 2mb - 64mb sdram bank 1 2mb - 64mb external i/o bank 0 256 kb - 4mb external i/o bank 1 256 kb - 4mb external i/o bank 2 256 kb - 4mb external i/o bank 3 256 kb - 4mb reserved reserved 8kb 512kb (fixed) 0x7ff8.0000 0x0000 _0000 0x7fff_ffff reserved 0x7fe0_0000 reserved 512kb (fixed) 0x7ff0_0000 ebi space rom/flash 256 kb - 4mb sdram bank 0 2mb - 64mb sdram bank 1 2mb - 64mb external i/o bank 0 256 kb - 4mb external i/o bank 1 256 kb - 4mb external i/o bank 2 256 kb - 4mb external i/o bank 3 256 kb - 4mb on-chip ram 4kb,4kb on-chip apb peripherals 8kb 512kb (fixed) 0xfff8_0000 0x8000 _0000 0xffff_ffff reserved 0xffe0_0000 on-chip ahb peripherals 512kb (fixed) 0xfff0_0000 ebi space figure 6.2.1 system memory map free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 27 - revision a2 table 6.2.1 on-chip peripherals memory map base address description ahb peripherals 0xfff0_0000 product identifier register (pdid) 0xfff0_0004 arbitration contro l register (arbcon) 0xfff0_0008 pll control register 0(pllcon0) 0xfff0_000c clock select register (clksel) 0xfff0_0010 pll control register 1 (pllcon1) 0xfff0_0014 audio i 2 s clock control register (i 2 sckcon) 0xfff0_0020 irq wakeup control register (irqwakeupcon) 0xfff0_0024 irq wakeup flag register (irqwakeflag) 0xfff0_0028 power manager control register (pmcon) 0xfff0_0030 usb transceiver control register (usbtxrcon) 0xfff0_1000 ebi control register (ebicon) control registers 0xfff0_1004 rom/flash (romcon) control registers 0xfff0_1008 sdram bank 0 ? 1 control registers 0xfff0_1018 external i/o 0 ? 3 control registers 0xfff0_2000 cache controller control registers 0xfff0_3000 ethernet mac contro ller control registers 0xfff0_4000 gdma 0 ? 1 control registers 0xfff0_5000 usb host controller control registers 0xfff0_6000 usb device controller control registers 0xfff0_9000 ac97/i2s controller control registers apb peripherals 0xfff8_0000 uart 0 (tx, rx for console) 0xfff8_0100 uart 1 (tx, rx, for bluetooth) 0xfff8_0200 uart 2 (bluetooth ct s, rts/ irda tx, rx) 0xfff8_0300 uart 3 (micro-pri nt dtr, dts, tx, rx) 0xfff8_1000 timer 0 ? 1, wdog timer 0xfff8_2000 interrupt controller 0xfff8_3000 gpio 0xfff8_6000 i 2 c-0 control registers 0xfff8_6100 i 2 c-1 control registers 0xfff8_6200 usi control registers 0xfff8_7000 pulse width modulati on (pwm) control registers 0xfff8_8000 keypad interface control register (kpi) 0xfff8_9000 ps2 control registers free datasheet http:///
W90N745cd/W90N745cdg - 28 - 6.2.3 address bus generation the W90N745 address bus generation is depended on the required data bus width of each memory bank. the data bus width is determined by dbwd bits in each bank?s control register. the maximum accessible memory size of each external io bank is 4m bytes. table 6.2.2 address bus generation guidelines data bus external address pins width a [20:0] maximum accessible memory size 8-bit a20 ? a0 (internal) 2m bytes 16-bit a21 ? a1 (internal) 2m half-words 6.2.4 data bus connection with external memory 6.2.4.1. memory formats the W90N745 can be configured as big endian or littl e endian mode by pull up or down the external data bus d14 pin. if d14 is pull up, then it is a li ttle endian mode, otherwise, it is a big endian mode. little endian in little endian format, the lowest addressed byte in a wo rd is considered the least significant byte of the word and the highest addressed byte is the most signi ficant. so the byte at address 0 of the memory system connects to data lines 7 through 0. for a word aligned address a, figure 6.2.2 shows how the half-word at addresses a and a+2, and the bytes at addresses a, a+1, a+2, and a+3 map on to each other when d14 pin is high. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 half-word at address a half-word at address a+2 byte at address a+1 byte at address a byte at address a+3 byte at address a+2 figure 6.2.2 little endian addresses of bytes and half-words within half words free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 29 - revision a2 big endian in big endian format, the W90N745 stores the most si gnificant byte of a word at the lowest numbered byte, and the least significant byte at the highest-numbered byte. so the byte at address 0 of the memory system connects to data lines 31 through 24. for a word aligned address a, figure 6.2.3 shows how the half-word at addresses a and a+2, and the bytes at addresses a, a+1, a+2, and a+3 map on to each other when the d14 pin is low. 15 14 13 12 1110987654321 0 half-word at address a half-word at address a+2 byte at address a byte at address a+1 byte at address a+2 byte at address a+3 figure 6.2.3 big endian addresses of bytes and half-words within half words 6.2.4.2. connection of external memory with various data width the system diagram for W90N745 connecting with the ex ternal memory is shown in figure 6.2.4. below tables (table 6.2.3 through table 6.2.14) show the program/data path betw een cpu register and the external memory using little / big endian and word/half-word/byte access. figure 6.2.4 address/data bus connection with external memory free datasheet http:///
W90N745cd/W90N745cdg - 30 - figure 6.2.5 cpu registers read/write with external memory table 6.2.3 and table 6.2.4 using big-endian and word access, program/data path between register and external memory wa = address whose lsb is 0,4,8,c x = don?t care nwbe [1-0] / sdqm [1-0] = a means active and u means inactive table 6.2.3 word access write operation with big endian access operation write operation (cpu register ? external memory) xd width half word byte bit number cpu reg data 31 0 abcd 31 0 abcd sa wa wa bit number sd 31 0 ab cd 31 0 a b c d bit number ed 15 0 ab 15 0 cd 7 0 a 7 0 b 7 0 c 7 0 d xa wa wa+2 wa wa+1 wa+2 wa+3 nwbe [1-0] / sdqm [1-0] aa aa xa xa xa xa bit number xd 15 0 ab 15 0 cd 7 0 a 7 0 b 7 0 c 7 0 d bit number ext. mem data 15 0 ab 15 0 cd 7 0 a 7 0 b 7 0 c 7 0 d timing sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 31 - revision a2 table 6.2.4 word access read operation with big endian access operation read operation (cpu register external memory) xd width half word byte bit number cpu reg data 31 0 cdab 31 0 dcba sa wa wa bit number sd 31 0 cd ab 31 0 d c b a bit number ed 31 0 cd xx 31 0 cd ab 31 0 d x x x 31 0 d c x x 31 0 d c b x 31 0 d c b a xa wa wa+2 wa wa+1 wa+2 wa+3 sdqm [1-0] aa aa xa xa xa xa bit number xd 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a bit number ext. mem data 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a timing sequence 1st read 2 nd read 1st read 2nd read 3rd read 4th read table 6.2.5 and table 6.2.6 using big-endian and half-word access, program/dat a path between register and external memory. ha = address whose lsb is 0,2, 4,6,8,a,c,e x = don?t care nwbe [1-0] / sdqm [1-0] = a means active and u means inactive table 6.2.5 half-word access writ e operation with big endian access operation write operation (cpu register ? external memory) xd width half word byte bit number cpu reg data 31 0 abcd 31 0 abcd sa ha ha bit number sd 31 0 cd cd 31 0 cd cd 31 0 cd cd bit number ed 31 0 cd cd 7 0 c 7 0 d xa ha ha ha+1 nwbe [1-0] / sdqm [1-0] aa xa xa bit number xd 15 0 cd 7 0 c 7 0 d bit number ext. mem data 15 0 cd 7 0 c 7 0 d timing sequence 1st write 2nd write free datasheet http:///
W90N745cd/W90N745cdg - 32 - table 6.2.6 half-word access read operation with big endian access operation read operation (cpu register external memory) xd width half word byte bit number cpu reg data 15 0 cd 15 0 dc sa ha ha bit number sd 15 0 cd 15 0 dc bit number ed 15 0 cd 15 0 dx 15 0 dc xa ha ha ha+1 sdqm [1-0] aa xa xa bit number xd 15 0 cd 7 0 d 7 0 c bit number ext. mem data 15 0 cd 7 0 d 7 0 c timing sequence 1st read 2nd read table 6.2.7 and table 6.2.8 using big-endian and byte access, program/data path between register and external memory. ba = address whose lsb is 0,1, 2,3,4,5,6,7,8,9,a,b,c,d,e,f bal = address whose lsb is 0,2,4,6,8,a,c,e bau = address whose lsb is 1,3,5,7,9,b,d,f free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 33 - revision a2 table 6.2.7 byte access write operation with big endian access operation write operation (cpu register external memory) xd width half word byte bit number cpu reg data 31 0 abcd 31 0 abcd sa bal bau ba bit number sd 31 0 d d d d 31 0 d d d d 31 0 d d d d bit number ed 15 8 d 7 0 d 7 0 d xa bal bal ba nwbe [1-0] / sdqm [1-0] au ua xa bit number xd 15 0 d x 15 0 x d 7 0 d bit number ext. mem data 15 8 d 7 0 d 7 0 d timing sequence table 6.2.8 byte access read operation with big endian access operation read operation (cpu register external memory) xd width half word byte bit number cpu reg data 7 0 c 7 0 d 7 0 d sa bal bau ba bit number sd 7 0 c 7 0 d 7 0 d bit number ed 7 0 c 15 8 d 7 0 d xa bal bal ba sdqm [1-0] au ua xa bit number xd 15 0 cd 15 0 cd 7 0 d bit number ext. mem data 15 0 cd 7 0 d timing sequence free datasheet http:///
W90N745cd/W90N745cdg - 34 - table 6.2.9 and table 6.2.10 using little-endian and word access, program/dat a path between register and external memory wa = address whose lsb is 0,4,8,c x = don?t care nwbe [1-0] / sdqm [1-0] = a means active and u means inactive table 6.2.9 word access write operation with little endian access operation write operation (cpu register ? external memory) xd width half word byte bit number cpu reg data 31 0 abcd 31 0 abcd sa wa wa bit number sd 31 0 ab cd 31 0 a b c d bit number ed 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a xa wa wa+2 wa wa+1 wa+2 wa+3 nwbe [1-0] / sdqm [1-0] aa aa xa xa xa xa bit number xd 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a bit number ext. mem data 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a timing sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write table 6.2.10 word access read operation with little endian access operation read operation (cpu register external memory) xd width half word byte bit number cpu reg data 31 0 abcd 31 0 abcd sa wa wa bit number sd 31 0 ab cd 31 0 a b c d bit number ed 31 0 xx cd 31 0 ab cd 31 0 x x x d 31 0 x x c d 31 0 x b c d 31 0 a b c d xa wa wa+2 wa wa+1 wa+2 wa+3 sdqm [1-0] aa aa xa xa xa xa bit number xd 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a bit number ext. mem data 15 0 cd 15 0 ab 7 0 d 7 0 c 7 0 b 7 0 a timing sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 35 - revision a2 table 6.2.11 and table 6.2.12 using little-endian and half-word access, program/dat a path between register and external memory. ha = address whose lsb is 0,2, 4,6,8,a,c,e x = don?t care nwbe [1-0] / sdqm [1-0] = a means active and u means inactive table 6.2.11 half-word access write operation with little endian access operation write operation (cpu register ? external memory) xd width half word byte bit number cpu reg data 31 0 abcd 31 0 abcd sa ha ha bit number sd 31 0 cd cd 31 0 cd cd 31 0 cd cd bit number ed 31 0 cd cd 7 0 d 7 0 c xa ha ha ha+1 nwbe [1-0] / sdqm [1-0] aa xa xa bit number xd 15 0 cd 7 0 d 7 0 c bit number ext. mem data 15 0 cd 7 0 d 7 0 c timing sequence 1st write 2nd write table 6.2.12 half-word access read operation with little endian access operation read operation (cpu register external memory) xd width half word byte bit number cpu reg data 15 0 cd 15 0 cd sa ha ha bit number sd 15 0 cd 15 0 cd bit number ed 15 0 cd 15 0 xd 15 0 cd xa ha ha ha+1 sdqm [1-0] aa xa xa bit number xd 15 0 cd 7 0 d 7 0 c bit number ext. mem data 15 0 cd 7 0 d 7 0 c timing sequence 1st read 2nd read free datasheet http:///
W90N745cd/W90N745cdg - 36 - table 6.2.13 and table 6.2.14 using little-endian and byte access, program/dat a path between register and external memory. ba = address whose lsb is 0,1, 2,3,4,5,6,7,8,9,a,b,c,d,e,f bal = address whose lsb is 0,2,4,6,8,a,c,e bau = address whose lsb is 1,3,5,7,9,b,d,f table 6.2.13 byte access write ope ration with little endian access operation write operation (cpu register ? external memory) xd width half word byte bit number cpu reg data 31 0 abcd 31 0 abcd sa bal bau ba bit number sd 31 0 d d d d 31 0 d d d d 31 0 d d d d bit number ed 7 0 d 15 8 d 7 0 d xa bal bal ba nwbe [1-0] / sdqm [1-0] ua au xa bit number xd 15 0 x d 15 0 d x 7 0 d bit number ext. mem data 7 0 d 15 8 d 7 0 d timing sequence table 6.2.14 byte access read ope ration with little endian access operation read operation (cpu register external memory) xd width half word byte bit number cpu reg data 7 0 d 7 0 c 7 0 d sa bal bau ba bit number sd 7 0 d 7 0 c 7 0 d bit number ed 7 0 d 7 0 c 7 0 d xa bal bal ba sdqm [1-0] ua au xa bit number xd 15 0 cd 15 0 cd 7 0 d bit number ext. mem data 15 0 cd 7 0 d timing sequence free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 37 - revision a2 6.2.5 bus arbitration the W90N745?s internal function blocks or external devices can request mastersh ip of the system bus and then hold the system bus in order to perform data transfers. because the design of W90N745 bus allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal units or external devices simult aneously request bus mastership. when bus mastership is granted to an internal function block or an external device, other pending requests are not acknowledged until the previous bus master has released the bus. W90N745 supports two priority modes, the fixed priority mode and the rotate priority mode , depends on the arbcon register prtmod bit setting. 6.2.5.1. fixed priority mode in fixed priority mode ( prtmod =0, default value), to facilitate bus ar bitration, priorities are assigned to each internal W90N745 function block. the bus contro ller arbitration requests for the bus mastership according to these fixed priorities. in the event of contention, mastership is granted to the function block with the highest assigned priority. these pr iorities are listed in table 6.2.15. W90N745 allows raising arm core priority to second if an unmasked interrupt occurred. if ipen bit, bit 1 of the arbitration control register (arbcon) , is set to ?0?, the priority of arm core is fixed to lowest. if ipen bit is set to ?1? and if no unmasked interrupt r equest, then the arm core?s priority is still lowest and the ipact =0, bit 2 of the arbitration control register (arbcon) if there is an unmasked interrupt request, then the arm core?s priority is raised to first and ipact =1. if ipen is set, an interrupt handler will normally clear ipact at the end of the interrupt routine to allow an alternate bus master to regain the bus; however, if ipen is cleared, no additional action need be taken in the interrupt handler. the ipact bit can be read and written. writing with ?0?, the ipact bit is cleared, but it will be no effect as writing with ?1?. table 6.2.15 bus priorities for arbi tration in fixed priority mode bus function block priority ipact = 0 ipen = 1 and ipact = 1 1 (highest) audio controller (ac97 & i2s) arm core 2 general dma0 audio controller (ac97 & i2s) 3 general dma1 general dma0 4 emc dma general dma1 5 usb host emc dma 6 usb device usb host 7(lowest) arm core usb device free datasheet http:///
W90N745cd/W90N745cdg - 38 - 6.2.5.2. rotate priority mode in rotate priority mode ( prtmod =1), the ipen and ipact bits have no function (i.e. can be ignored). W90N745 uses a round robin arbitration scheme ensures that all bus masters have equal chance to gain the bus and that a retracted master does not lock up the bus. 6.2.6 power management W90N745 provide three power management scenar ios to reduce power consumption. the peripherals? clocks can be enabled / disabled indi vidually by controlling the co-responding bit in clksel control register. software can turn-off the unused modules? clocks to saving the unnecessary power consumption. it also provides idle and power-down modes to reduce power consumption. figure 6.2.6 W90N745 system clock generation diagram free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 39 - revision a2 idle mode if the idle bit in power management control regist er (pmcon) is set, the arm core clock source will be halted, the arm core will not go forward. the ahb or apb clocks still active except the clock to cache controller and arm are stopped. W90N745 will ex it idle state when nirq or nfiq from any peripheral is revived; like keypad, timer overflow in terrupts and so on. the memory controller can also be forced to enter idle state if both midle and idle bits are set. software must switch sdram into self-refresh mode before forcing memory to enter idle mode. fout (pll) hclk idle_state mclk (arm) hclk (cache) idle period hclk (memc) case1. idle=1, pd=0, midle=0 figure 6.2.7 clock management for system idle mode fout (pll) hclk idle_state mclk (arm) hclk (cache) idle period hclk (memc) case2. idle=1, pd=0, midle=1 figure 6.2.8 clock management for system and memory idle mode free datasheet http:///
W90N745cd/W90N745cdg - 40 - power down mode this mode provides the minimum power consumpti on. when the W90N745 system is not working or waiting an external event, software can write pd bit ?1 ? to turn off all the clocks includes system crystal oscillator to let arm core enter sleep mode. in th is state, all peripherals are also in sleep mode since the clock source is stopped. W90N745 will exit power down state when nirq/nfiq is detected. W90N745 provides external interrupt nirq[1:0], keypad, and usb device interfaces to wakeup the system clock. hclk (cache) case3. idle=0, pd=1, midle=0 extal idle _state pd_state 65536 clocks hclk wake up by pheripheral's interrupts figure 6.2.9 clock management for system power down mode and wake up free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 41 - revision a2 6.2.7 power-on setting after power on reset, there are eight power-on setting pins to configure W90N745 system configuration. power-on setting pin internal system clock select d15 little/big endian mode select d14 boot rom/flash data bus width d [13:12] default: pull-down in normal operation d9 default: pull-up in normal operation d8 d15 pin internal system clock select if pin d15 is pull-down, the external clock from extal pin is served as internal system clock. if pin d15 is pull-up, the pll output clo ck is used as internal system clock. d14 pin little/big endian mode select if pin d14 is pull-down, the external memory format is big endian mode. if pin d14 is pull-up, the external memory format is little endian mode. d [13:12] boot rom/flash data bus width d [13:12] bus width pull-down pull-down 8-bit pull-down pull-up 16-bit pull-up pull-down reserved pull-up pull-up reserved 6.2.8 system manager control registers map register address r/w description reset value pdid 0xfff0_0000 r product ident ifier register 0xx090_0745 arbcon 0xfff0_0004 r/w arbitrati on control register 0x0000_0000 pllcon0 0xfff0_0008 r/w pll cont rol register 0 0x0000_2f01 clksel 0xfff0_000c r/w clock select register 0x1fff_3fx8 pllcon1 0xfff0_0010 r/w pll c ontrol register 1 0x0001_0000 i2sckcon 0xfff0_0014 r/w audio i 2 s clock control register 0x0000_0000 irqwakecon 0xfff0_0020 r/w irq wakeup control register 0x0000_0000 irqwakeflag 0xffff_0024 r/w irq wakeup flag register 0x0000_0000 pmcon 0xfff0_0028 r/w power manager control register 0x0000_0000 usbtxrcon 0xfff0_0030 r/w usb transce iver control register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 42 - product identifier register pdid this register is read only and lets so ftware can use it to recognize certai n characteristics of the chip id and the version number. register address r/w description reset value pdid 0xfff0_0000 r product ident ifier register 0xx090_0745 31 30 29 28 27 26 25 24 package version 23 22 21 20 19 18 17 16 chpid 15 14 13 12 11 10 9 8 chpid 7 6 5 4 3 2 1 0 chpid bits description [31:30] package package type select these two bits are power-on setting latched from pin d[9:8] package [31:30] package type 0 1 128-pin package [29:24] version version of chip [23:0] chipid the chip identifier of W90N745 is 0x090.0745 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 43 - revision a2 arbitration control register (arbcon) register address r/w description reset value arbcon 0xfff0_0004 r/w arbitration control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ipact ipen prtmod bits description [31:3] reserved - [2] ipact interrupt priority active. when ipen =?1?, this bit will be set when the arm core has an unmasked interrupt request. this bit is available only when the prtmod =0. [1] ipen interrupt priority enable bit 0 = the arm core has the lowest priority. 1 = enable to raise the arm core priority to second this bit is available only when the prtmod =0. [0] prtmod priority mode select 0 = fixed priority mode (default) 1 = rotate priority mode free datasheet http:///
W90N745cd/W90N745cdg - 44 - pll control register0 pllcon0 W90N745 provides two clock generation options ? cr ystal and oscillator. the external clock via extal(15 m) minput pin as the reference clock input of pll module. the external clock can bypass the pll and be used to the internal system clo ck by pull-down the data d15 pin. using pll ?s output clock for the internal system clock, d15 pin must be pull-up. register address r/w description reset value pllcon 0xfff0_0008 r/w pll control register 0x0000_2f01 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pwden 15 14 13 12 11 10 9 8 fbdv 7 6 5 4 3 2 1 0 fbdv otdv indv bits description [31:17] reserved - [16] pwden power down mode enable 0 = pll is in normal mode (default) 1 = pll is in power down mode [15:7] fbdv pll vco output clock feedback divider feedback divider divides the output clock from vco of pll. [6:5] otdv pll output clock divider otdv [6:5] divided by 0 0 1 0 1 2 1 0 2 1 1 4 [4:0] indv pll input clock divider input divider divides the input reference clock into the pll. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 45 - revision a2 input divider (nr) pfd feedback divider (nf) charge pump vco output divider (no) clock divider & selector extal eclks otdv[1:0] clks[2:0] 1 0 pll internal system clock indv[4:0] fbdv[8:0] 48mhz gen 480mhz 0 1 usbcks usb module fin fout gp0 figure 6.2.10 system pll block diagram the formula of output clock of pll is: f out = f in n o nr nf 1 ? ? f out output clock of output divider f in external clock into the input divider nr input divider value (nr = indv + 2) nf feedback divider value (nf = fbdv + 2) no output divider value (no = otdv) free datasheet http:///
W90N745cd/W90N745cdg - 46 - clock select register (clksel) register address r/w description reset value clksel 0xfff0_000c r/w clock select register 0x1fff_7fx8 31 30 29 28 27 26 25 24 reserved ps2 kp i reserved ssp 23 22 21 20 19 18 17 16 uart3 uart2 uart1 i 2 c1 i 2 c0 reserved pwm ac97 15 14 13 12 11 10 9 8 usbcks usbd gdma reserved emc reserved wdt 7 6 5 4 3 2 1 0 usbh timer uart eclks clks reset bits description [31:29] reserved - [28] ps2 ps2 controller clock enable bit 0 = disable ps2 controller clock 1 = enable ps2 controller clock [27] kpi keypad controller clock enable bit 0 = disable keypad controller clock 1 = enable keypad controller clock [26] reserved - [25] reserved - [24] usi usi controller clock enable bit 0 = disable usi controller clock 1 = enable usi controller clock [23] uart3 uart3 controller clock enable bit 0 = disable uart3 controller clock 1 = enable uart3 controller clock [22] uart2 uart2 controller clock enable bit 0 = disable uart2 controller clock 1 = enable uart2 controller clock [21] uart1 uart1 controller clock enable bit 0 = disable uart1 controller clock 1 = enable uart1 controller clock free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 47 - revision a2 continued. bits description [20] i 2 c1 i 2 c1 controller clock enable bit 0 = disable i 2 c1 controller clock 1 = enable i 2 c1 controller clock [19] i 2 c0 i 2 c0 controller clock enable bit 0 = disable i 2 c0 controller clock 1 = enable i 2 c0 controller clock [18] reserved - [17] pwm pwm controller clock enable bit 0 = disable pwm controller clock 1 = enable pwm controller clock [16] ac97 audio controller clock enable bit 0 = disable ac97 controller clock 1 = enable ac97 controller clock [15] usbcks usb host/device 48mhz clock source select bit 0 = usb clock 48mhz input from internal pll (480mhz/10) 1 = usb clock 48mhz input from external gpio0 pin, this pin direction must set to input. [14] usbd usb device clock enable bit 0 = disable usb device controller clock 1 = enable usb device controller clock [13] gdma gdma controller clock enable bit 0 = disable gdma clock 1 = enable gdma clock [12] reserved - [11] reserved - [10] emc emc controller clock enable bit 0 = disable emc controller clock 1 = enable emc controller clock [9] reserved - [8] wdt wdt clock enable bit 0 = disable wdt counting clock 1 = enable wdt counting clock free datasheet http:///
W90N745cd/W90N745cdg - 48 - continued. bits description [7] usbh usb host clock enable bit 0 = disable usb host controller clock 1 = enable usb host controller clock [6] timer timer clock enable bit 0 = disable timer clock 1 = enable timer clock [5] uart0 uart0 controller clock enable bit 0 = disable uart0 controller clock 1 = enable uart0 controller clock [4] eclks external clock select 0 = external clock from extal pin is used as system clock 1 = pll output clock is used as system clock after power on reset, the content of eclks is the power-on setting value. you can program this bit to change the system clock source. [3:1] clks pll output clock select clks [3:1] system clock 0 0 0 58.594 khz* 0 0 1 24 mhz 0 1 0 48 mhz 0 1 1 60 mhz 1 0 0 80 mhz 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved note: 1. this values are based on pll output(fout) is 480mhz. 2. when 24mhz ~ 80mhz is selected, the eclks bit must be set to 1. 3. about 58.594khz setting, two st eps are needed. first, clear eclks bit, and then clear clks. [0] reset software reset bit this is a software reset control bit. set logic 1 to generate an internal reset pulse. this bit is auto -clear to logic 0 at the end of the reset pulse. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 49 - revision a2 pll control register 1 pllcon1 W90N745 provides extra pll to prov ide 12.288/16.934 mhz clock source to audio controller. it uses the same 15mhz crystal clock input source with system pll mentioned above. register address r/w description reset value pllcon1 0xfff0_0010 r/w pll control register 1 0x0001_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pwden1 15 14 13 12 11 10 9 8 fbdv1 7 6 5 4 3 2 1 0 fbdv1 otdv1 indv1 bits description [31:17] reserved - [16] pwden1 pll1 power down enable 0 = pll1 is in normal mode 1 = pll1 is in power down mode (default) [15:7] fbdv1 pll1 vco output clock feedback divider feedback divider divides the output clock from vco of pll1. [6:5] otdv1 pll1 output clock divider otdv1 [6:5] divided by 0 0 1 0 1 2 1 0 2 1 1 4 [4:0] indv1 pll1 input clock divider input divider divides the input reference clock into the pll1. free datasheet http:///
W90N745cd/W90N745cdg - 50 - input divider (nr) pfd feedback divider (nf) charge pump vco output divider (no) extal otdv1[1:0] pll1 indv1[4:0] fbdv1[8:0] 480mhz fin fout to audio controller figure 6.2.11 audio pll block diagram the formula of output clock of pll is: f out = f in no nr nf 1 ? ? f out output clock of output divider f in external clock into the input divider nr input divider value (nr = indv1 + 2) nf feedback divider value (nf = fbdv1 + 2) no output divider value (no = otdv1) free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 51 - revision a2 i 2 s clock control register (i2sckcon) register address r/w description reset value i2sckcon 0xfff0_0014 r/w i2s pll clock control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved i 2 spllen 7 6 5 4 3 2 1 0 prescale bits description [31:9] reserved - [8] i2spllen i 2 s pll clock source enable set this bit will enable pll1 clock output to audio i 2 s clock input. 1 = enable pll1 clock source for audio i 2 s 0 = disable pll1 clock source for audio i 2 s [7:0] prescale the pll1 is used by i 2 s, if in use, software can using this prescaler to generate an appropriate clock nearly 12.288m or 16.934m. the clock is generated as below, and if prescale =0, the pll_audio is the same frequency as fout ?pll_audio = pll_fout/(prescale +1)? free datasheet http:///
W90N745cd/W90N745cdg - 52 - irq wakeup control register (irqwakecon) register address r/w description reset value irqwakecon 0xfff0_0020 r/w irq wakeup control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved irqwakeuppol reserved irqwakeupen bits description [31:6] reserved [5] irqwakeuppol[1] nirq1 wake up polarity 1 = nirq1 is high level wake up 0 = nirq1 is low level wake up [4] irqwakeuppol[0] nirq0 wake up polarity 1 = nirq0 is high level wake up 0 = nirq0 is low level wake up [3:2] reserved [1] irqwakeupen[1] nirq1 wake up enable bit 1 = nirq1 wake up enable 0 = nirq1 wake up disable [0] irqwakeupen[0] nirq0 wake up enable bit 1 = nirq0 wake up enable 0 = nirq0 wake up disable free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 53 - revision a2 irq wakeup flag register (irqwakeflag) register address r/w description reset value irqwakeflag 0xfff0_0024 r/w irq wakeup flag register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved irqwakeflag this register is used to record the wakeup event, a fter clock recovery, software should check these flags to identify which nirq is used to wakeup the system. and clear the flags in irq interrupt sevice routine. bits description [31:2] reserved - [1] irqwakeflag[1] nirq1 wake up flag 1 = chip is waked up by nirq1 0 = no active [0] irqwakeflag[0] nirq0 wake up flag 1 = chip is waked up by nirq0 0 = no active free datasheet http:///
W90N745cd/W90N745cdg - 54 - power management control register (pmcon) register address r/w description reset value pmcon 0xfff0_0028 r/w power management control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved midle pd idle bits description [31:3] reserved [2] midle memory controller idle enable setting both midle and idle bits high will let memory controller enter idle mode, the clock source of memory controller will be halted while arm core enter idle mode. 1=memory controller will be forced into idle mode, (clock of memory controller will be halted), when idle bit is set. 0 = memory controller still active when idle bit is set. note: software must let sdram enter self-refresh mode before enable this function because sdram mclk will be stopped. [1] pd power down enable setting this bit high will let w 90n745 enter power saving mode. th e clock source 15m crystal oscillator and plls are stopped to generat e clock. user can use nirq[3:0], keypad and external reset to wakeu p W90N745. 1 = enable power down 0 = disable [0] idle idle mode enable setting this bit high will let arm core enter power saving mode. th e peripherals can still keep working if the clock enable bit in clksel i s set. any nirq or nfiq to arm core will let arm core to exit idl e state. 1 = idle mode 0 = disable free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 55 - revision a2 usb transceiver control register (usbtxrcon) register address r/w description reset value usbtxrcon 0xfff0_0030 r/w usb transceiver control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved usbhnd bits description [31:1] reserved - [0] usbhnd usbhnd[0]: usb transceiver control there are two usb1.1 built-in transceivers for data transmission. one is dedicated for usb host and the ot her is shared with usb device. software can program this bit to switch the transceiver path. 1 = host 0 = device free datasheet http:///
W90N745cd/W90N745cdg - 56 - 6.3 external bus interface 6.3.1 ebi overview W90N745 supports external bus interface ( ebi ), which controls the acce ss to the external memory (rom/flash, sdram) and external i/o devices. the ebi has seven chip selects to select one rom/flash bank, two sdram banks, and four exte rnal i/o banks.the address bus is 21 bits. it supports 8-bit, 16-bit external data bus width for each bank. the ebi has the following functions y sdram controller y ebi control register y rom/flash interface y external i/o interface y external bus mastership 6.3.2 sdram controller the sdram controller module within w90n 745 contains configuration registers timing control registers common control register and other logic to provide 8 16 bits sdram interface with a single 8 16 bits sdram device or two 8-bit devices wired to give a 16-bit data path. the maximum size of each bank is 64m bytes, and maximum memory size can span up to 128mb. the sdram controller has the following features y supports up to 2 external sdram banks y maximum size of each bank is 64m bytes y 8 16-bit data interface y programmable cas latency 1 2 and 3 y fixed burst length 1 y sequential burst type y auto refresh mode and self refresh mode y adjustable refresh rate y power up sequence free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 57 - revision a2 6.3.2.1. sdram components supported table 6.3.1 sdram supported by W90N745 size type banks row addressing column addressing 2mx8 2 ra0~ra10 ca0~ca8 16m bits 1mx16 2 ra0~ra10 ca0~ca7 8mx8 4 ra0~ra11 ca0~ca8 64m bits 4mx16 4 ra0~ra11 ca0~ca7 16mx8 4 ra0~ra11 ca0~ca9 128m bits 8mx16 4 ra0~ra11 ca0~ca8 32mx8 4 ra0~ra12 ca0~ca9 256m bits 16mx16 4 ra0~ra12 ca0~ca8 ahb bus address mapping to sdram bus note : * indicates the signal is not used; ** indicate s the signal is fixed at logic 0 and is not used; the haddr prefixes have been omi tted on the following tables. a14 ~ a0 are the address pins of the W90N745 ebi interface; a14 and a13 are the bank se lect signals of sdram. free datasheet http:///
W90N745cd/W90N745cdg - 58 - sdram data bus width: 16-bit total type r x c r/c a14 (bs1) a13 (bs0) a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 16m 2mx8 11x9 r ** 10 ** 10 * 21 20 19 18 17 16 15 14 13 12 11 c ** 10 ** 10 * ap 24 * 98765 4 3 21 16m 1mx16 11x8 r ** 9 ** 9 * 10 20 19 18 17 16 15 14 13 12 11 c ** 9 ** 9 * ap 24 * 9 * 8765 4 3 21 64m 8mx8 12x9 r 10 11 10 * 22 21 20 19 18 17 16 15 14 13 12 23 c 10 11 10 * 22 * ap 24 * 98765 4 3 21 64m 4mx16 12x8 r 10 9 10 * 22 21 20 19 18 17 16 15 14 13 12 11 c 10 9 10 * 22 * ap 24 * 23 * 8765 4 3 21 128m 16mx8 12x10 r 10 11 10 * 22 21 20 19 18 17 16 15 14 13 12 23 c 10 11 10 * 22 * ap 24 9 8 7 6 5 4 3 21 128m 8mx16 12x9 r 10 11 10 * 22 21 20 19 18 17 16 15 14 13 12 23 c 10 11 10 * 22 * ap 24 * 98765 4 3 21 256m* 32mx8 13x10 r 10 11 23 22 21 20 19 18 17 16 15 14 13 12 24 c 10 11 23 * 22 * ap 25 * 98765 4 3 21 256m 16mx16 13x9 r 10 11 23 22 21 20 19 18 17 16 15 14 13 12 24 c 10 11 23 * 22 * ap 25 * 9 8765 4 3 21 sdram data bus width: 8-bit total type r x c r/c a14 (bs1) a13 (bs0) a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 16m 2mx8 11x9 r ** 9 ** 9 * 20 19 18 17 16 15 14 13 12 11 10 c ** 9 ** 9 * ap 23 * 87654 3 2 1 0 64m 8mx8 12x9 r 9 10 9 * 21 20 19 18 17 16 15 14 13 12 11 22 c 9 10 9 * 21 * ap 23 * 87654 3 2 1 1 128m 16mx8 12x10 r 9 10 9 * 21 20 19 18 17 16 15 14 13 12 11 22 c 9 10 9 * 21 * ap 2387654 3 2 1 0 256m 32mx8 13x10 r 9 10 22 21 20 19 18 17 16 15 14 13 12 11 23 c 9 10 22 * 21 * ap 24 87654 3 2 1 0 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 59 - revision a2 6.3.2.2. sdram power up sequence the sdram must be initialized predefined manner after power on.W90N745 sdram controller automatically executes the commands needed for init ialion and set the mode register of each bank to default value. the default value is ? burst length = 1 ? burst type = sequential (fixed) ? cas latency = 2 ? write burst length = burst (fixed) the value of mode register can be changed afte r power up sequence by setting the value of corresponding bank?s configuration register ? length ? and ? latency ? bits and set the mrset bit enable to execute the mode register set command. 6.3.2.3. sdram interface mclk mcke nscs[1:0] nsras nscas nswe nsdqm[1:0] a[20:0] d[15:0] a[10:0] dq[[15:0] dqm[1:0] nwe ncas nras ncs bs0 bs1 clk cke W90N745 a13 a14 a[10:0] nscs0 sdram 32mb 512kx4x16 nsdqm[1:0] figure 6.3.1 sdram interface free datasheet http:///
W90N745cd/W90N745cdg - 60 - 6.3.3 ebi control registers map register address r/w description reset value ebicon 0xfff0_1000 r/w ebi control register 0x0001_0000 romcon 0xfff0_1004 r/w rom/flash control register 0x0000_0xfc sdconf0 0xfff0_1008 r/w sdram bank 0 configuration register 0x0000_0800 sdconf1 0xfff0_100c r/w sdram bank 1 configuration register 0x0000_0800 sdtime0 0xfff0_1010 r/w sdram bank 0 timing control register 0x0000_0000 sdtime1 0xfff0_1014 r/w sdram bank 1 timing control register 0x0000_0000 ext0con 0xfff0_1018 r/w external i/o 0 control register 0x0000_0000 ext1con 0xfff0_101c r/w external i/o 1 control register 0x0000_0000 ext2con 0xfff0_1020 r/w external i/o 2 control register 0x0000_0000 ext3con 0xfff0_1024 r/w external i/o 3 control register 0x0000_0000 ckskew 0xfff0_1f00 r/w clock skew control register (for testing) 0xxxxx_0038 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 61 - revision a2 ebi control register (ebicon) register address r/w description reset value ebicon 0xfff0_1000 r/w ebi control register 0x0001_0000 31 30 29 28 27 26 25 24 reserved exbe3 exb e2 exbe1 exbe0 23 22 21 20 19 18 17 16 reserved refen refmod clken 15 14 13 12 11 10 9 8 refrat 7 6 5 4 3 2 1 0 refrat waitvt little bits description [31:27] reserved [27] exbe3 external io bank 3 byte enable this function is used for some devices that with high and low bytes enable signals to control which byte will be write or mask data output when read. for this kind device, so ftware can set this bit high to implement this function. detail pi n interconnection is showed as figure 6.3.8. 1 = nwbe[1:0] pin is byte enable signals, nwe will be used as write strobe signal to sram. 0 = nwbe[1:0] pin is byte write strobe signal. [26] exbe2 external io bank 2 byte enable the bit function description is the same as exbe3 above. 1 = nwbe[1:0] pin is byte enable signals, nwe will be used as write strobe signal to sram. 0 = nwbe[1:0] pin is byte write strobe signal. [25] exbe1 external io bank 1 byte enable the bit function description is the same as exbe3 above. 1 = nwbe[1:0] pin is byte enable signals, nwe will be used as write strobe signal to sram 0 = nwbe[1:0] pin is byte write strobe signal free datasheet http:///
W90N745cd/W90N745cdg - 62 - continued. bits description [24] exbe0 external io bank 0 byte enable this bit function description is the same as exbe3 above. 1 = nwbe[1:0] pin is byte enable signals, nwe will be used as write strobe signal to sram 0 = nwbe[1:0] pin is byte write strobe signal [23:19] reserved - [18] refen enable sdram refresh cycle for sdram bank0 & bank1 this bit set will start the auto-refresh cycle to sdram. the refresh rate is according to refrat bits. 1 = enable refresh function 0 = disable refresh function [17] refmod refresh mode of sdram for sdram bank defines the refresh mode type of external sdram bank software can write this bit ?1? to force sdram enter self-refresh mode. 0 = auto refresh mode 1 = self refresh mode note: if any read/write to sdram occurs then this bit will be cleared to ?0? by hardware automatically and sdram will enters auto-refresh mode. [16] clken clock enable for sdram enables the sdram clock enable ( cke ) control signal 0 = disable (power down mode) 1 = enable default [15:3] refrat refresh count value for sdram the sdram controller automatically provides an auto refresh cycle for every refresh period programmed into the refrat bits when the refen bit of each bank is set the refresh period is calculated as fmclk value period = free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 63 - revision a2 continued. bits description [2:1] waitvt valid time of nwait signal W90N745 recognizes the nwait signal at the next ?nth? mclk rising edge after the noe or nwbe active cycle. waitvt bits determine the n. waitvt [2:1] nth mclk 0 0 1 0 1 2 1 0 3 1 1 4 [0] little little endian mode after power on reset, the content of little is the power-on setting value from d14 pin. if pin d14 is pu ll-down, the external memory format is big endian mode. if pin d14 is pull- up, the external memory format is little endian mode. for more detail, refer to power-on setting of system manager. note: this bit is read only. free datasheet http:///
W90N745cd/W90N745cdg - 64 - rom/flash control register romcon register address r/w description reset value romcon 0xfff0_1004 r/w rom/flash control register 0x0000_0xfc 31 30 29 28 27 26 25 24 basaddr 23 22 21 20 19 18 17 16 basaddr size 15 14 13 12 11 10 9 8 reserved tpa 7 6 5 4 3 2 1 0 tacc btsize pgmode bits description [31:19] basaddr base address pointer of rom/flash bank the start address is calculated as rom/flash bank base pointer << 18. the base address pointer together with the ? size ? bits constitutes the whole address range of each bank. [18:16] size the size of rom/flash memory size [10:8] byte 0 0 0 256k 0 0 1 512k 0 1 0 1m 0 1 1 2m 1 0 0 4m 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved [15:12] reserved - free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 65 - revision a2 continued. bits description [11:8] tpa page mode access cycle time tpa[11:8] mclk tpa[11:8] mclk 0 0 0 0 1 1 0 0 0 10 0 0 0 1 2 1 0 0 1 12 0 0 1 0 3 1 0 1 0 14 0 0 1 1 4 1 0 1 1 16 0 1 0 0 5 1 1 0 0 18 0 1 0 1 6 1 1 0 1 20 0 1 1 0 7 1 1 1 0 22 0 1 1 1 8 1 1 1 1 24 [7:4] tacc access cycle time tacc[11:8] mclk tacc[11:8] mclk 0 0 0 0 1 1 0 0 0 10 0 0 0 1 2 1 0 0 1 12 0 0 1 0 3 1 0 1 0 14 0 0 1 1 4 1 0 1 1 16 0 1 0 0 5 1 1 0 0 18 0 1 0 1 6 1 1 0 1 20 0 1 1 0 7 1 1 1 0 22 0 1 1 1 8 1 1 1 1 24 [3:2] btsize boot rom/flash data bus width this rom/flash bank is designed for a boot rom. basaddr bits determine its start address. the exter nal data bus width is determined by the data bus signals d [13:12] power-on setting. btsize [3:2] bus width d [13:12] bus width 0 0 8-bit pull-down pull-down 8-bit 0 1 16-bit pull-down pull-up 16-bit 1 0 reserved pull-up pull-down reserved 1 1 reserved pull-up pull-up reserved [1:0] pgmode page mode configuration pgmode [1:0] mode 0 0 normal rom 0 1 4 word page 1 0 8 word page 1 1 16 word page free datasheet http:///
W90N745cd/W90N745cdg - 66 - figure 6.3.2 rom/flash read operation timing figure 6.3.3 rom/flash page read operation timing free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 67 - revision a2 configuration registers sdconf0/1 the configuration registers enable software to se t a number of operating parameters for the sdram controller. there are two conf iguration registers sdconf0 sdconf1 for sdram bank 0 bank 1 respectively. each bank can hav e a different configuration. register address r/w description reset value sdconf0 0xfff0_1008 r/w sdram bank 0 configuration register 0x0000_0800 sdconf1 0xfff0_100c r/w sdram bank 1 configuration register 0x0000_0800 31 30 29 28 27 26 25 24 basaddr 23 22 21 20 19 18 17 16 basaddr reserved 15 14 13 12 11 10 9 8 mrset reserved autopr latency reserved 7 6 5 4 3 2 1 0 compbk dbwd column size bits description [31:19] basaddr base address pointer of sdram bank 0/1 the start address is calculated as sdram bank 0/1 base pointer << 18. the sdram base address poi nter together with the ? size ? bits constitutes the whole address range of each sdram bank. [18:16] reserved - [15] mrset sdram mode register set command for sdram bank 0/1 this bit set will issue a mode register set command to sdram. [14] reserved - [13] autopr auto pre-charge mode of sdram for sdram bank 0/1 enable the auto pre-charge functi on of external sdram bank 0/1 0 = auto pre-charge 1 = no auto pre-charge [12:11] latency the cas latency of sdram bank 0/1 defines the cas latency of external sdram bank 0/1 latency [12:11] mclk 0 0 1 0 1 2 1 0 3 1 1 reversed free datasheet http:///
W90N745cd/W90N745cdg - 68 - continued. bits description [10:8] reserved - [7] compbk number of component bank in sdram bank 0/1 indicates the number of component bank (2 or 4 banks) in external sdram bank 0/1. 0 = 2 banks 1 = 4 banks [6:5] dbwd data bus width for sdram bank 0/1 indicates the external data bus width connect with sdram bank 0/1 if dbwd = 00, the assigned sdra m access signal is not generated i.e. disable. dbwd [6:5] bits 0 0 bank disable 0 1 8-bit (byte) 1 0 16-bit (half-word) 1 1 reversed [4:3] column number of column address bits in sdram bank 0/1 indicates the number of column address bits in external sdram bank 0/1. column [4:3] bits 0 0 8 0 1 9 1 0 10 1 1 reversed [2:0] size size of sdram bank 0/1 indicates the memory size of external sdram bank 0/1 size [2:0] size of sdram byte 0 0 0 bank disable 0 0 1 2m 0 1 0 4m 0 1 1 8m 1 0 0 16m 1 0 1 32m 1 1 0 64m 1 1 1 reversed free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 69 - revision a2 timing control registers sdtime0/1 W90N745 offers the flexible timing control regist ers to control the generation and processing of the control signals and can achieve y ou use different speed of sdram register address r/w description reset value sdtime0 0xfff0_1010 r/w sdram bank 0 timing control register 0x0000_0000 sdtime1 0xfff0_1014 r/w sdram bank 1 timing control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved trcd 7 6 5 4 3 2 1 0 trdl trp tras bits description [31:11] reserved - [10:8] trcd sdram bank 0/1, /ras to /cas delay trcd [10:8] mclk 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 [7:6] trdl sdram bank 0/1, last data in to pre-charge command trdl [7:6] mclk 0 0 1 0 1 2 1 0 3 1 1 4 free datasheet http:///
W90N745cd/W90N745cdg - 70 - continued. bits description [5:3] trp sdram bank 0/1, row pre-charge time trp [5:3] mclk 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 [2:0] tras sdram bank 0/1, row active time tras [2:0] mclk 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 71 - revision a2 figure 6.3.4 access timing 1 of sdram figure 6.3.5 access timing 2 of sdram free datasheet http:///
W90N745cd/W90N745cdg - 72 - external i/o control registers ext0con ? ext3con the W90N745 supports an external device control without glue logic. it is very cost effective because address decoding and control signals timing logic are not needed. using these control registers you can configure special external i/o devic es for providing the low cost ex ternal devices control solution. register address r/w description reset value ext0con 0xfff0_1018 r/w external i/o 0 control register 0x0000_0000 ext1con 0xfff0_101c r/w external i/o 1 control register 0x0000_0000 ext2con 0xfff0_1020 r/w external i/o 2 control register 0x0000_0000 ext3con 0xfff0_1024 r/w external i/o 3 control register 0x0000_0000 31 30 29 28 27 26 25 24 basaddr 23 22 21 20 19 18 17 16 basaddr size 15 14 13 12 11 10 9 8 adrs tacc tcoh 7 6 5 4 3 2 1 0 tacs tcos dbwd bits description [31:11] basaddr base address pointer of external i/o bank 0~3 the start address of each external i/o bank is calculated as ? basaddr? base pointer << 18. each external i/o bank base address pointer together with the ? size ? bits constitutes the whole address range of each external i/o bank. [18:16] size the size of the external i/o bank 0~3 size [18:16] byte 0 0 0 256k 0 0 1 512k 0 1 0 1m 0 1 1 2m 1 0 0 4m 1 0 1 8m 1 1 0 reversed 1 1 1 reversed free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 73 - revision a2 continued. bits description [15] adrs address bus alignment for external i/o bank 0~3 when adrs is set, external address (a20~a0) bus is alignment to byte address format, that is, a0 is inter nal ahb address bus haddr[0] and a1 is ahb bus haddr[1] and so forth. and it ignores dbwd [1:0] setting. [14:11] tacc access cycles of external i/o bank 0~3 this parameter means nwe, nwbe and no e active time clock. detail timing diagram please refer to figure 6.3.6 and 6.3.7 tacc[14:11] mclk tacc[14:11] mclk 0 0 0 0 reversed 1 0 0 0 9 0 0 0 1 1 1 0 0 1 11 0 0 1 0 2 1 0 1 0 13 0 0 1 1 3 1 0 1 1 15 0 1 0 0 4 1 1 0 0 17 0 1 0 1 5 1 1 0 1 19 0 1 1 0 6 1 1 1 0 21 0 1 1 1 7 1 1 1 1 23 [10:8] tcoh chip selection hold time of external i/o bank 0~3 this parameters control nwbe and noe hold time. detail timing diagram please refer to figure 6.3.6 and 6.3.7 tcoh [10:8] mclk 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 free datasheet http:///
W90N745cd/W90N745cdg - 74 - continued. bits description [7:5] tacs address set-up before necs for external i/o bank 0~3 tacs [7:5] mclk 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 [4:2] tcos chip selection set-up time of external i/o bank 0~3 when rom/flash memory bank is c onfigured, the access to its bank stretches chip selection time before the noe or new signal is activated. tcos [4:2] mclk 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 [1:0] dbwd programmable data bus width for external i/o bank 0~3 dbwd [1:0] width of data bus 0 0 disable bus 0 1 8-bit 1 0 16-bit 1 1 reserved free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 75 - revision a2 figure 6.3.6 external i/o write operation timing figure 6.3.7 external i/o read operation timing free datasheet http:///
W90N745cd/W90N745cdg - 76 - figure 6.3.8 external io bank with 16-bit sram clock skew control register ckskew register address r/w description reset value ckskew 0xfff0_1f00 r/w clock skew control register 0xxxxx_0018 31 30 29 28 27 26 25 24 dlh_clk_ref 23 22 21 20 19 18 17 16 dlh_clk_ref 15 14 13 12 11 10 9 8 resvered swpon 7 6 5 4 3 2 1 0 dlh_clk_skew mclk_o_d free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 77 - revision a2 bits description [31:16] dlh_clk_ref latch dlh_clk clock tree by hclk positive edge the sdram mclk is generated by inse rting a delay (xor2) chain in hclk positive or negedge edge to adjust the mclk skew. so software can read these bits to expore mclk and hclk relationship. [31:24] is used for positive edge and [23:16] is for negedge edge. [15:9] reserved - [8] swpon sdram initialization by software set this bit ?1? will issue a sdram power on default setting command sequence like system power on, this bit will be auto-clear by hardware while sdram initialization finish. [7:4] dlh_clk_skew data latch clock skew adjustment due to pc board loading or too m any devices connect to external address and data bus, it may causes sdram can not work correctly at high frequency (usually, > 80mhz) software can control mclk_o_d[3:0] to adjust address and data bus to adjust setup/hold time. dlh_clk_skew[7:4] gate delay dlh_clk_skew[7:4] gate delay 0 0 0 0 p-0 1 0 0 0 n-0 0 0 0 1 p-1 1 0 0 1 n-1 0 0 1 0 p-2 1 0 1 0 n-2 0 0 1 1 p-3 1 0 1 1 n-3 0 1 0 0 p-4 1 1 0 0 n-4 0 1 0 1 p-5 1 1 0 1 n-5 0 1 1 0 p-6 1 1 1 0 n-6 0 1 1 1 p-7 1 1 1 1 n-7 note : p-x means data latched clock shift ?x? gates delays by refer mclko positive edge, n-x means data latched clock shift ?x? gates delays by refer mclko negative edge. free datasheet http:///
W90N745cd/W90N745cdg - 78 - continued. bits description [3:0] mclk_o_d mclk output delay adjustment mclk_o_d [3:0] gate dela y mclk_o_d [3:0] gate dela y 0 0 0 0 p-0 1 0 0 0 n-0 0 0 0 1 p-1 1 0 0 1 n-1 0 0 1 0 p-2 1 0 1 0 n-2 0 0 1 1 p-3 1 0 1 1 n-3 0 1 0 0 p-4 1 1 0 0 n-4 0 1 0 1 p-5 1 1 0 1 n-5 0 1 1 0 p-6 1 1 1 0 n-6 0 1 1 1 p-7 1 1 1 1 n-7 note: ?p-x? means mclko shift ?x? gates delay by refer hclk positive edge, ?n-x? means mclko shi ft ?x? gates delay by refer hclk negative edge. mclk is the output pin of mclko, which is an internal signal on chip. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 79 - revision a2 6.4 cache controller the W90N745 incorporates a 4kb instruction cache, 4kb data cache and 8 words write buffer. the i- cache and d-cache have similar organization except the ca che size. to raise the cache-hit ratio, these two caches are configured two-way set associative addressing. each cache has four words cache line size. when a miss occurs, four words must be fe tched consecutively from external memory. the replacement algorithm is a lru (least recently used). if disabling the i-cache / d-cache, these cac he memories can be treated as on-chip ram. the W90N745 also provides a write buffer to improve sy stem performance. the write buffer can buffer up to eight words of data. 6.4.1 on-chip ram if i-cache or d-cache is disabled, it can be served as on-chip ram. if d-cache is disabled, there has 4kb on-chip ram, its start addre ss is 0xffe01000. if i-cache is dis abled, there has 4kb on-chip ram and the start address of this ram is 0xffe00000. if bot h the i-cache and d-cache are disabled, it has 8kb on-chip ram starting from 0xffe00000. the size of on-chip ram is depended on the i-cache and d-cache enable bits icaen , dcaen in cache control register (cahcon). table 6.4.1 the size and start address of on-chip ram on-chip ram icaen dcaen size start address 0 0 8kb 0xffe0_0000 0 1 4kb 0xffe0_0000 1 0 4kb 0xffe0.1000 1 1 unavailable 6.4.2 non-cacheable area although the cache affects the entir e 2gb system memory, it is so metimes necessary to define non- cacheable areas when the consistency of data stor ed in memory and the cache must be ensured. to support this, the W90N745 provides a non-cacheable area control bit in the address field, a[31]. if a[31] in the rom/flash, sdram, or external i/o bank?s access address is ?0?, then the accessed data is cacheable. if the a [31] value is ?1?, the accessed data is non-cacheable. free datasheet http:///
W90N745cd/W90N745cdg - 80 - 6.4.3 instruction cache the instruction cache (i-cache) is a 4k bytes two- way set associative cache. the cache organization is 128 sets, two lines per set, and four words per line. cache lines are aligned on 4-word boundaries in memory. the cache access cycle begins with an instruct ion request from the instruction unit in the core. in the case of a cache hit, the instruction is delivered to the instruction unit. in case of a cache miss, the cache initiates a burst read cycle on the internal bus with the address of the requested instruction. the first word received from the bus is the requested instru ction. the cache forwards this instruction to the instruction unit of the core as soon as it is received from the internal bus. a cache line is then selected to receive the data that will be coming from the bus. a l east recently used (lru) replacement algorithm is used to select a line when no empty lines are availabl e. when i-cache is disabled, the cache memory is served as 4kb on-chip ram. the i- cache is always disabled on reset. the following is a list of the instruction cache features y 4k bytes instruction cache y two-way set associative y four words in a cache line y lru replacement policy y lockable on a per-line basis y critical word first, burst access instruction cache operation on an instruction fetch, bits 10-4 of the instruction?s address point into the cache to retrieve the tags and data of one set. the tags from both ways are then compared against bits 30-11 of the instruction?s address. if a match is found and the matched entry is valid , then it is a cache hit. if neither tags match nor the matched tag is not valid, it is a cache miss. instruction cache hit in case of a cache hit, bits 3-2 of the instruction address is used to select one word from the cache line whose tag matches. the instruction is immediately transferred to the instruction unit of the core. instruction cache miss on an instruction cache miss, the addr ess of the missed instruction is dr iven on the internal bus with a 4- word burst transfer read request. a cache line is t hen selected to receive the data that will be coming from the bus. the selection algorithm gives first priority to invalid lines. if neither of the two lines in the selected set is invalid, then the least recently us ed line is selected for replacement. locked lines are never replaced. the transfer begins with the word reques ted by the instruction unit (critical word first), followed by the remaining words of the line, then by the word at the beginning of the lines (wraparound). instruction cache flushing the W90N745 does not support external memory snooping. therefore, if self-modi fying code is written, the instructions in the i-cache may become invalid . the entire i-cache can be flushed by software in one operation, or can be flushed one li ne at a time by setting the cahcon register bit flhs or flha with the icah bit is set. as flushing the cache line, the ? v ? bit of the line is cleared to ?0?. the i-cache is automatically flushed during reset. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 81 - revision a2 instruction cache load and lock the W90N745 supports a cache-locking feature that can be used to lock critical sections of code into i- cache to guarantee quick access. lockdown can be perfo rmed with a granularity of one cache line. the smallest space, which can be locked down, is 4 words. after a line is locked, it operates as a regular instruction sram. lines locked are not replaced during misses and not affected by flush per line command. to load and lock instruction, the following sequence should be followed: 1. write the start address of the instructions to be locked into cahadr register. 2. set ldlk and icah bits in the cahcon register. 3. increased the address by 16 and written into cahadr register. 4. set ldlk and icah bits in the cahcon register. 5. repeat the steps 3 and 4, until the desired instructions are all locked. when using i-cache load and lock command, there are some notes should be cared. y the programs executing load and lock operation should be held in a non- cacheable area of memory. y the cache should be enabled and interrupts should be disabled. y software must flush the cache before execute load and lock to ensure that the code to be locked down is not already in the cache. instruction cache unlock the unlock operation is used to unlock previous ly locked cache lines. after unlock, the ? l ? bit of the line is cleared to ?0?. W90N745 has two unlock command, unlock line and unlock all. the unlock line operation is performed on a cache line granul arity. in case the line is found in the cache, it is unlocked and starts to operate as a regular valid cache line. in case the line is not found in the cache, no operation is done and the command terminat es with no exception. to unlock one line the following unlock line sequence should be followed: 1. write the address of the line to be unlocked into the cahadr register. 2. set the ulks and icah bits in the cahcon register. the unlock all operation is used to unlock the whole i-cache. this operation is performed on all cache lines. in case a line is locked, it is unlocked and star ts to operate as regular valid cache line. in case a line is not locked or if it is invalid, no operation is performed. to unlock the whole cache, set the ulka and icah bits. free datasheet http:///
W90N745cd/W90N745cdg - 82 - 6.4.4 data cache the W90N745 data cache (d-cache) is a 4kb two-way set associative cache. the cache organization is 128 sets, two lines per set, and four words per line. cache lines are aligned on 4-word boundaries in memory. the cache is designed for buffer write-through mode of operation and a least recently used (lru) replacement algorithm is used to select a line when no empty lines are available. when d-cache is disabled, the cache me mory is served as 4kb on-chip ram. the d-cache is always disabled on reset. the following is a list of the data cache features y 4k bytes data cache y two-way set associative y four words in a cache line y lru replacement policy y lockable on a per-line basis y critical word first, burst access y buffer write-through mode y 8 words write buffer y drain write buffer data cache operation on a data fetch, bits 10-4 of the data?s address point into the cache to retrieve the tags and data of one set. the tags from both ways are then compared agains t bits 30-11 of the data?s address. if a match is found and the matched entry is valid, then it is a cac he hit. if neither tags match nor the matched tag is not valid, it is a cache miss. data cache read read hit on a cache hit, the requested word is immediately transferred to the core. read miss a line in the cache is selected to hold the data, which will be fetched from memory. the selection algorithm gives first priority to invalid lines and if both lines are invalid the line in way zero is selected first. if neither of the two candidate lines in the selected set is invalid, then one of the lines is selected by the lru algorithm to replace. the tr ansfer begins with the aligned word containing the missed data (critical word first), followed by the rema ining word in the line, then by the word at the beginning of the line (wraparound). as the missed word is received from the bus, it is delivered directly to the core. data cache write as buffer write-through mode, store operations alwa ys update memory. the buffer write-through mode is used when external memory and internal cache images must always agree. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 83 - revision a2 write hit data is written into both the cache and write buffer. the processor then continues to access the cache, while the cache controller simultaneously downloads the contents of the write buffer to main memory. this reduces the effective write memory cycle time from the time required for a main memory cycle to the cycle time of the high-speed cache. write miss data is only written into write buffer, not to the cache (write no allocate). data cache flushing the W90N745 allows flushing of the data cache under software control. the data cache may be invalidated through writing flush line ( flhs ) or flush all ( flha ) commands to the cahcon register. flushing the entire d-cache also flushed any lock ed down code. as flushing the data cache, the ? v ? bit of the line is cleared to ?0?. the d-ca che is automatically flushed during reset. data cache load and lock the W90N745 supports a cache-locking feature that can be used to lock critical sections of data into d- cache to guarantee quick access. lockdown can be perfo rmed with a granularity of one cache line. the smallest space, which can be locked down, is 4 words. after a line is locked, it operates as a regular instruction sram. the locked lines are not replaced dur ing misses and it is not affected by flush per line command. to load and lock data, the following sequence should be followed: 1. write the start address of the data to be locked into cahadr register. 2. set ldlk and dcah bits in the cahcon register. 3. increased the address by 16 and written into cahadr register. 4. set ldlk and dcah bits in the cahcon register. 5. repeat the steps 3 and 4, until the desired data are all locked. when using d-cache load and lock command, there are some notes should be cared. y the programs executing load and lock operation should be held in a non- cacheable area of memory. y the cache should be enabled and interrupts should be disabled. y software must flush the cache before execute load and lock to ensure that the data to be locked down is not already in the cache. data cache unlock the unlock operation is used to unlock previous ly locked cache lines. after unlock, the ? l ? bit of the line is cleared to ?0?. W90N745 has two unlock command, unlock line and unlock all. the unlock line operation is performed on a cache line granul arity. in case the line is found in the cache, it is unlocked and starts to operate as a regular valid cache line. in case the line is not found in the cache, no operation is done and the command terminat es with no exception. to unlock one line the following unlock line sequence should be followed: 1. write the address of the line to be unlocked into the cahadr register. 2. set the ulks and dcah bits in the cahcon register. free datasheet http:///
W90N745cd/W90N745cdg - 84 - the unlock all operation is used to unlock the whole d-cache. this operation is performed on all cache lines. in case a line is locked, it is unlocked and star ts to operate as regular valid cache line. in case a line is not locked or if it is invalid, no operation is performed. to unlock the whole cache, set the ulka and dcah bits. 6.4.5 write buffer the W90N745 provides a write buffer to improve syst em performance. the write buffer can buffer up to eight words of data. the write buffe r may be enabled or be disabled via the wrben bit in the cahcnf register, and the buffer is disabled and flushed on reset. drain write buffer to force data, this is in write buffer, to be written to external main memory. this operation is useful in real time applications where the processor needs to be sure that a write to a peripheral has completed before program execution continues. to perform this command, you can set the drwb and dcah bits in cahcon register. 6.4.6 cache control registers map register address r/w description reset value cahcnf 0xfff0_2000 r/w cache configuration register 0x0000_0000 cahcon 0xfff0_2004 r/w cache control register 0x0000_0000 cahadr 0xfff0_2008 r/w cache address register 0x0000_0000 ctest0 0xfff6_0000 r/w cache test register 0 0x0000_0000 ctest1 0xfff6_0004 r cache test register 1 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 85 - revision a2 configuration register (cahcnf) cache controller has a configuration register to enable or disable the i-cache, d-cache, and write buffer. register address r/w description reset value cahcnf 0xfff0_2000 r/w cache configuration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved wrben dcaen icaen bits description [31:3] reserved - [2] wrben write buffer enable write buffer is disabled after reset. 1 = enable write buffer 0 = disable write buffer [1] dcaen d-cache enable d-cache is disabled after reset. 1 = enable d-cache 0 = disable d-cache [0] icaen i-cache enable i-cache is disabled after reset. 1 = enable i-cache 0 = disable i-cache free datasheet http:///
W90N745cd/W90N745cdg - 86 - control register (cahcon) cache controller supports one control register used to control the following operations. y flush i-cache and d-cache y load and lock i-cache and d-cache y unlock i-cache and d-cache y drain write buffer these command set bits in cahcon register are auto-clear bits. as the end of executi on, that command set bit will be cleared to ?0? automatically. register address r/w description reset value cahcon 0xfff0_2004 r/w cache control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 drwb ulks ulka ldlk flhs flha dcah icah bits description [31:8] reserved - [7] drwb drain write buffer forces write buffer data to be written to main memory. [6] ulks unlock i-cache/d-cache single line unlocks the i-cache/d-cache per line. both way and addr bits in cahadr register must be specified. [5] ulka unlock i-cache/d-cache entirely unlocks the entire i-cache/d-cache, the lock bit ? l ? will be cleared to 0. [4] ldlk load and lock i-cache/d-cache loads the instruction or data from external memory and locks into cache. both way and addr bits in cahadr register must be specified. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 87 - revision a2 continued. bits description [3] flhs flush i-cache/d-cache single line flushes the entire i-cache/d-cache per line. both way and addr bits in cahadr register must be specified. [2] flha flush i-cache/d-cache entirely to flush the entire i-cache/d-cac he, also flushes any locked-down code. if the i-cache/d-cache c ontains locked down code, the programmer must flush lines individually [1] dcah d-cache selected when set to ?1?, the command set is executed with d-cache. [0] icah i-cache selected when set to ?1?, the command set is executed with i-cache. note when using the flha or ulka command, you can set both icah and dcah bits to execute entire i-cache and d-cache flushing or unlocking. but, flhs and ulks commands can only be executed with a cache line specified by cahadr register in i-cache or d-cache at a time. if you set both icah and dcah bits, and set flhs or ulks command bit, it will be treated as an invalid command and no operation is done and the comm and terminates with no exception. the drain write buffer operation is only for d-cache. to per form this operation, you must set drwb and dcah bits. if the icah bit is set when using drwb command, it will be an invalid command and no operation is done and the command ter minates with no exception. free datasheet http:///
W90N745cd/W90N745cdg - 88 - address register (cahadr) W90N745 cache controller supports one address regist er. this address register is used with the command set in the control register ( cahcon ) by specifying instru ction/data address. register address r/w description reset value cahadr 0xfff0_2008 r/w cache address register 0x0000_0000 31 30 29 28 27 26 25 24 way addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 7 6 5 4 3 2 1 0 addr bits description [31] way way selection 0 = way0 is selected 1 = way1 is selected [30:0] addr the absolute addre ss of instruction or data free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 89 - revision a2 cache test register 0 (ctest0) cache test control register that configures the cache and tag ram test ing enable or disable. in addition, this register controls the built-in- self-test (bist) function of sram. register address r/w description reset value ctest0 0xfff6_0000 r/w cache test register 0 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 bisten reserved bst_gp3 bst_gp2 bst_gp1 bst_gp0 7 6 5 4 3 2 1 0 reserved catest bits description [31:16] reserved - [15] bisten bist mode enable when set to ?1?, bist mode will be enabled, the selected memory groups begins to be tested by bist. [14:12] reserved - [11] bist_gp3 memory group 3 is selected to test by bist when set to ?1?, memory group 3, including data cache tag ram way 0 and way 1, are selected to be tested by bist. [10] bist_gp2 memory group 2 is selected to test by bist when set to ?1?, memory group 2, including program cache tag ram way 0 and way 1, are selected to be tested by bist. [9] bist_gp1 memory group 1 is selected to test by bist when set to ?1?, memory group 1, including data cache ram way 0 and way 1, are selected to be tested by bist. [8] bist_gp0 memory group 0 is selected to test by bist when set to ?1?, memory group 0, including program cache ram way 0 and way 1, are selected to be tested by bist. [7:0] reserved - ** note : the 4 memory groups can be selected and tested simultaneously by bist. free datasheet http:///
W90N745cd/W90N745cdg - 90 - cache test register 1 (ctest1) cache test register that will be read back to provide the status of cache ram bist. whether the bist is finish and all of bank of sram are tested successfully will be presented in this register. register address r/w description reset value ctest1 0xfff6_0004 r cache test register 1 0x0000_0000 31 30 29 28 27 26 25 24 finish reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 bfail7 bfail6 bfail5 bfail4 bfail3 bfail2 bfail1 bfail0 bits description [31] finish bist completed this bit is ?0? initially. when bist mode enabled, this bit will be ?1? after bist test completed. the values of bfail0-7 are valid only after finish = 1. [30:8] reserved - [7] bfail7 bist test fail for data cache tag ram way 1 if this bit equals to ?1?, it indicates the data cache tag ram for way 1 is tested fail by bist. ?0? means the test is passed. [6] bfail6 bist test fail for data cache tag ram way 0 if this bit equals to ?1?, it indicates the data cache tag ram for way 0 is tested fail by bist. ?0? means the test is passed. [5] bfail5 bist test fail for instruction cache tag ram way 1 if this bit equals to ?1?, it indicate s the instruction cache tag ram for way 1 is tested fail by bist. ?0? means the test is passed. [4] bfail4 bist test fail for instruction cache tag ram way 0 if this bit equals to ?1?, it indicate s the instruction cache tag ram for way 0 is tested fail by bist. ?0? means the test is passed. [3] bfail3 bist test fail for data cache ram way 1 if this bit equals to ?1?, it indicates the data cache ram for way 1 is tested fail by bist. ?0? means the test is passed. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 91 - revision a2 continued. bits description [2] bfail2 bist test fail for data cache ram way 0 if this bit equals to ?1?, it indicates the data cache ram for way 0 is tested fail by bist. ?0? means the test is passed. [1] bfail1 bist test fail for instruction cache ram way 1 if this bit equals to ?1?, it indicates the instruction cache ram for way 1 is tested fail by bist. ?0? means the test is passed. [0] bfail0 bist test fail for instruction cache ram way 0 if this bit equals to ?1?, it indicates the instruction cache ram for way 0 is tested fail by bist. ?0? means the test is passed. free datasheet http:///
W90N745cd/W90N745cdg - 92 - 6.5 ethernet mac controller overview the W90N745 provides an ethernet mac controller (emc) for lan application. this emc has its dma controller, transmit fifo, and receive fifo. the ethernet mac controller consists of ieee 802. 3/ethernet protocol engine with internal cam function for ethernet mac address recognition, trans mit-fifo, receive-fifo, tx/rx state machine controller and status controller. the emc only suppor ts rmii (reduced mii) inte rface to connect with phy operating on 50mhz ref_clk. features y supports ieee std. 802.3 csma/cd protocol. y supports both half and full duplex for 10m/100m bps operation. y supports rmii interface. y supports mii management function. y supports pause and remote pause function for flow control. y supports long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception. y supports 16 entries cam function fo r ethernet mac address recognition. y supports internal loop back mode for diagnostic. y supports 256 bytes embedded transmit and receive fifo. y supports dma function. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 93 - revision a2 6.5.1 emc functional description mii management state machine the mii management function of emc is compliant to ieee 802.3 std. through the mii management interface, software can access the control and stat us registers of the external phy chip. tow programmable register miid (mac mii m anagement data register) and miida (mac mii management data control and address register) ar e for mii management function. set the bit busy of miida register will trigger the mii management state machine. after t he mii management cycle is finished, the busy bit will be cleared automatically. media access control (mac) the function of W90N745 mac fully meets the requi rements defined by the i eee802.3u specification. the following paragraphs will describe the frame st ructure and the operation of the transmission and receive. the transmission data frame sent from the trans mit dma will be encapsulated by the mac before transmitting onto the mii bus. the sent data will be assembled with the preamble, the start frame delimiter (sfd), the frame check sequence and the padding for enforcing those less than 64 bytes to meet the minimum size frame and crc sequence. t he out going frame format will be as following 1 10101010 --- 10101010 10101011 d0 d1 d2 - dn padding crc31 crc30 --- crc0 as mentioned by the above format, the preamble is a consecutive 7-byte long with the pattern ?10101010? and the sfd is a one byte 10101011 data. the padding data will be all 0 value if the sent data frame is less than 64 bytes. the padding disable function specified in the bit p of the transmit descriptor is used to control if the mac needs to pad data at the end of frame data or not when the transmitted data frame is less than 64 bytes. the padding data will not be appended if the padding disable bit is set to be high. the bits crc0 ... crc31 are the 32 bits cyclic redundancy check (crc) sequence. the crc encoding is defined by the following polynomial specified by the ieee802.3. this 32 bits crc appending function will be disabled if the i nhibit crc of the transmission descriptor is set to high. the mac also performs many other transmission func tions specified by the ieee802.3, including the inter-frame spacing function, collision detecti on, collision enforcement, collision back off and retransmission. the collision back-off timer is a func tion of the integer slot time, 512 bit times. the number of slot times to delay between the current transmissions attempts to the next attempt is determined by a uniformly distribut ed random integer algorithm specif ied by the ieee802.3. the mac performs the receive functions s pecified by the ieee 802.3 including the address recognition function, the frame check sequence validation, the frame disassembly, framing and collision filtering. free datasheet http:///
W90N745cd/W90N745cdg - 94 - emc descriptors a link-list data structure named as descriptor is used to keep the control, status and data information of each frame. through the descripto r, cpu and emc exchange the information for frame reception and transmission. two different descriptors are defined in W90N745. one named as rx descriptor for frame reception and the other names as tx descriptor for fr ame transmission. each rx descriptor consists of four words. there is much information kept in the descriptors and details are described as below. 6.5.1.1. rx buffer descriptor 3 1 3 0 2 9 1 6 1 5 0 o rx status receive byte count receive buffer starting address bo reserved next rx descriptor starting address rx descriptor word 0 31 30 29 28 27 26 25 24 owner reserved 23 22 21 20 19 18 17 16 reserved rp alie rxgd ptle reserved crce rxintr 15 14 13 12 11 10 9 8 rbc 7 6 5 4 3 2 1 0 rbc owner [31:30]: ownership the ownership field defines which one, the cpu or em c, is the owner of each rx descriptor. only the owner has right to modify the rx descriptor and the others can read the rx descriptor only. 00: the owner is cpu 01: undefined 10: the owner is emc 11: undefined if the o=2?b10 indicates the emc rxdma is the ow ner of rx descriptor and the rx descriptor is available for frame reception. after the fram e reception completed, if the frame needed nat translation, emc rxdma modify ownership field to 2?b11. otherwise, the ownership field will be modified to 2?b00. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 95 - revision a2 if the o=2?b00 indicates the cpu is the owner of rx descriptor. after the cpu completes processing the frame, it modifies the ownership field to 2?b10 and releases the rx descriptor to emc rxdma. rx status [29:16]: receive status this field keeps the status for frame reception. all status bits are updated by emc. in the receive status, bits 29 to 23 are undefined and reserved for the future. rp [22]: runt packet the rp indicates the frame stored in the data buffer pointed by rx descriptor is a short frame (frame length is less than 64 bytes). 1?b0: the frame is not a short frame. 1?b1: the frame is a short frame. alie [21]: alignment error the alie indicates the frame stored in the data buffe r pointed by rx descriptor is not a multiple of byte. 1?b0: the frame is a multiple of byte. 1?b1: the frame is not a multiple of byte. rxgd [20]: frame reception complete the rxgd indicates the frame reception has comp leted and stored in the dat a buffer pointed by rx descriptor. 1?b0: the frame reception not complete yet. 1?b1: the frame reception completed. ptle [19]: packet too long the ptle indicates the frame stored in the data buffe r pointed by rx descriptor is a long frame (frame length is greater than 1518 bytes). 1?b0: the frame is not a long frame. 1?b1: the frame is a long frame. crce [17]: crc error the crce indicates the frame stored in the data bu ffer pointed by rx descriptor incurred crc error. 1?b0: the frame doesn?t incur crc error. 1?b1: the frame incurred crc error. free datasheet http:///
W90N745cd/W90N745cdg - 96 - rxintr [16]: receive interrupt the rxintr indicates the frame stored in the data buffer pointed by rx descriptor caused an interrupt condition. 1?b0: the frame doesn?t cause an interrupt. 1?b1: the frame caused an interrupt. rbc [15:0]: receive byte count the rbc indicates the byte count of the frame stored in the data bu ffer pointed by rx descriptor. the four bytes crc field is also included in the receiv e byte count. but if the spcrc of register mcmdr is enabled, the four bytes crc field will be excluded from the receive byte count. rx descriptor word 1 31 30 29 28 27 26 25 24 rxbsa 23 22 21 20 19 18 17 16 rxbsa 15 14 13 12 11 10 9 8 rxbsa 7 6 5 4 3 2 1 0 rxbsa bo rxbsa [31:2]: receive buffer starting address the rxbsa indicates the starting address of the re ceive frame buffer. the rxbsa is used to be the bit 31 to 2 of memory address. in other words, t he starting address of the receive frame buffer always located at word boundary. bo [1:0]: byte offset the bo indicates the byte offset from rxbsa where the received frame begins to store. if the bo is 2?b01, the starting address where the received fr ame begins to store is rxbsa+2?b01, and so on. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 97 - revision a2 rx descriptor word 2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved the rx descriptor word 2 keeps obsolete inform ation for mac translation. therefore, these information bits are undefined and should be ignored. rx descriptor word 3 31 30 29 28 27 26 25 24 nrxdsa 23 22 21 20 19 18 17 16 nrxdsa 15 14 13 12 11 10 9 8 nrxdsa 7 6 5 4 3 2 1 0 nrxdsa nrxdsa [31:0]: next rx descriptor starting address the rx descriptor is a link-list data structure. consequently, nrxdsa is used to keep the starting address of the next rx descriptor. the bits [1:0] will be ignored by emc. so, all rx descriptor must locate at word boundary memory address. free datasheet http:///
W90N745cd/W90N745cdg - 98 - 6.5.1.2. tx buffer descriptor 3 1 3 0 1 6 1 5 3 2 1 0 o reserved i c p transmit buffer starting address bo tx status transmit byte count next tx descriptor starting address tx descriptor word 0 31 30 29 28 27 26 25 24 owner reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved inten crcapp paden owner [31]: ownership the ownership field defines which one, the cpu or em c, is the owner of each tx descriptor. only the owner has right to modify the tx descriptor and the other can read the tx descriptor only. 0: the owner is cpu 1: the owner is emc if the o=1?b1 indicates the emc txdma is the ow ner of tx descriptor and the tx descriptor is available for frame transmission. after the fr ame transmission completed, emc txdma modify ownership field to 1?b0 and return the ownership of tx descriptor to cpu. if the o=1?b0 indicates the cpu is the owner of tx descriptor. after the cpu prepares new frame to wait transmission, it modifies the ownership fiel d to 1?b1 and releases the tx descriptor to emc txdma. inten [2]: transmit interrupt enable the inten controls the interrupt trigger circuit a fter the frame transmission completed. if the inten is enabled, the emc will trigger interrupt after frame transmission completed. otherwise, the interrupt doesn?t be triggered. 1?b0: frame transmission interrupt is masked. 1?b1: frame transmission interrupt is enabled. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 99 - revision a2 crcapp [1]: crc append the crcapp control the crc append during frame tr ansmission. if crcapp is enabled, the 4-bytes crc checksum will be appended to frame at the end of frame transmission. 1?b0: 4-bytes crc appending is disabled. 1?b1: 4-bytes crc appending is enabled. paden [0]: padding enable the paden control the pad bits appending while t he length of transmission frame is less than 60 bytes. if paden is enabled, em c does the padding automatically. 1?b0: pad bits appending is disabled. 1?b1: pad bits appending is enabled. tx descriptor word 1 31 30 29 28 27 26 25 24 txbsa 23 22 21 20 19 18 17 16 txbsa 15 14 13 12 11 10 9 8 txbsa 7 6 5 4 3 2 1 0 txbsa bo txbsa [31:2]: transmit buffer starting address the txbsa indicates the starting address of the tr ansmit frame buffer. the txbsa is used to be the bit 31 to 2 of memory address. in other words, t he starting address of the transmit frame buffer always located at word boundary. bo [1:0]: byte offset the bo indicates the byte offset from txbsa wher e the transmit frame begins to read. if the bo is 2?b01, the starting address where the transmit fr ame begins to read is txbsa+2?b01, and so on. free datasheet http:///
W90N745cd/W90N745cdg - 100 - tx descriptor word 2 31 30 29 28 27 26 25 24 ccnt reserved sqe pau txha 23 22 21 20 19 18 17 16 lc txabt ncs exdef txcp reserved def txintr 15 14 13 12 11 10 9 8 tbc 7 6 5 4 3 2 1 0 tbc ccnt [31:28]: collision count the ccnt indicates the how many collision occurr ed consecutively during a packet transmission. if the packet incurred 16 consecutive collisions during transmission, the ccnt will be 4?h0 and bit txabt will be set to 1. sqe [26]: sqe error the sqe indicates the sqe error found at end of packet transmission on 10mbps half-duplex mode. the sqe error check will only be done while both bit ensqe of mcmdr is enabled and emc is operating on 10mbps half-duplex mode. 1?b0: no sqe error found at end of packet transmission. 1?b0: sqe error found at end of packet transmission. pau [25]: transmission paused the pau indicates the next normal packet transmission process will be paused temporally because emc received a pause control frame, or s/w set bit sdpz of mcmdr and make emc to transmit a pause control frame out. 1?b0: next normal packet transmission process will go on. 1?b1: next normal packet transmission process will be paused. txha [24]: transmission halted the txha indicates the next normal packet transmi ssion process will be halted because the bit txon of mcmdr is disabled be s/w. 1?b0: next normal packet transmission process will go on. 1?b1: next normal packet transmission process will be halted. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 101 - revision a2 lc [23]: late collision the lc indicates the collision occurred in the out side of 64 bytes collision window. this means after the 64 bytes of a frame has transmitted out to the net work, the collision still occurred. the late collision check will only be done while emc is operating on half-duplex mode. 1?b0: no collision occurred in the outside of 64 bytes collision window. 1?b1: collision occurred in the outside of 64 bytes collision window. txabt [22]: transmission abort the txabt indicates the packet incurred 16 consec utive collisions during transmission, and then the transmission process for this packet is aborted. t he transmission abort is only available while emc is operating on half-duplex mode. 1?b0: packet doesn?t incur 16 consecut ive collisions during transmission. 1?b1: packet incurred 16 consecutiv e collisions during transmission. ncs [21]: no carrier sense the ncs indicates the mii i/f signal crs doesn?t active at the start of or during the packet transmission. the ncs is only available wh ile emc is operating on half-duplex mode. 1?b0: crs signal actives correctly. 1?b1: crs signal doesn?t active at the st art of or during the packet transmission. exdef [20]: defer exceed the exdef indicates the frame waiting for transmission has deferred over 0.32768ms on 100mbps mode, or 3.2768ms on 10mbps mode. the deferral exceed check will only be done while bit ndef of mcmdr is disabled, and emc is operating on half-duplex mode. 1?b0: frame waiting for transmission has not deferred over 0.32768ms (100mbps) or 3.2768ms (10mbps). 1?b1: frame waiting for transmission has deferr ed over 0.32768ms (100mbps) or 3.2768ms (10mbps). txcp [19]: transmission complete the txcp indicates the packet tr ansmission has completed correctly. 1?b0: the packet transmission doesn?t complete. 1?b1: the packet transmission has completed. def [17]: transmission deferred the def indicates the packet transmission has defe rred once. the def is only available while emc is operating on half-duplex mode. 1?b0: packet transmission doesn?t defer. 1?b1: packet transmission has deferred once. free datasheet http:///
W90N745cd/W90N745cdg - 102 - txintr [16]: transmit interrupt the txintr indicates the packet transmission caused an interrupt condition. 1?b0: the packet transmission doesn?t cause an interrupt. 1?b1: the packet transmission caused an interrupt. tbc [15:0]: transmit byte count the tbc indicates the byte count of the frame stored in the data bu ffer pointed by tx descriptor for transmission. tx descriptor word 3 31 30 29 28 27 26 25 24 ntxdsa 23 22 21 20 19 18 17 16 ntxdsa 15 14 13 12 11 10 9 8 ntxdsa 7 6 5 4 3 2 1 0 ntxdsa ntxdsa [31:0]: next tx descriptor starting address the tx descriptor is a link-list data structure. consequently, ntxdsa is used to keep the starting address of the next tx descriptor. the bits [1:0] will be ignored by emc. so, all tx descriptor must locate at word boundary memory address. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 103 - revision a2 6.5.2 emc register mapping the emc implements many register s and the registers are separated into three types, the control registers, the status r egisters and diagnostic registers. the cont rol registers are used by s/w to pass control information to emc. the st atus registers are used to keep em c operation status for s/w. and, the diagnostic registers are used for debug only. emc registers register address r/w description reset value control registers (44) camcmr 0xfff0_3000 r/w ca m command register 0x0000_0000 camen 0xfff0_3004 r/w cam enable register 0x0000_0000 cam0m 0xfff0_3008 r/w cam0 most significant word register 0x0000_0000 cam0l 0xfff0_300c r/w cam0 least significant word register 0x 0000_0000 cam1m 0xfff0_3010 r/w cam1 most significant word register 0x0000_0000 cam1l 0xfff0_3014 r/w cam1 least significant word register 0x 0000_0000 cam2m 0xfff0_3018 r/w cam2 most significant word register 0x0000_0000 cam2l 0xfff0_301c r/w cam2 least significant word register 0x 0000_0000 cam3m 0xfff0_3020 r/w cam3 most significant word register 0x0000_0000 cam3l 0xfff0_3024 r/w cam3 least significant word register 0x 0000_0000 cam4m 0xfff0_3028 r/w cam4 most significant word register 0x0000_0000 cam4l 0xfff0_302c r/w cam4 least significant word register 0x 0000_0000 cam5m 0xfff0_3030 r/w cam5 most significant word register 0x0000_0000 cam5l 0xfff0_3034 r/w cam5 least significant word register 0x 0000_0000 cam6m 0xfff0_3038 r/w cam6 most significant word register 0x0000_0000 cam6l 0xfff0_303c r/w cam6 least significant word register 0x 0000_0000 cam7m 0xfff0_3040 r/w cam7 most significant word register 0x0000_0000 cam7l 0xfff0_3044 r/w cam7 least significant word register 0x 0000_0000 cam8m 0xfff0_3048 r/w cam8 most significant word register 0x0000_0000 cam8l 0xfff0_304c r/w cam8 least significant word register 0x 0000_0000 cam9m 0xfff0_3050 r/w cam9 most significant word register 0x0000_0000 cam9l 0xfff0_3054 r/w cam9 least significant word register 0x 0000_0000 cam10m 0xfff0_3058 r/w cam10 most significant word register 0x0000_0000 cam10l 0xfff0_305c r/w cam10 least significant word register 0x 0000_0000 cam11m 0xfff0_3060 r/w cam11 most significant word register 0x0000_0000 cam11l 0xfff0_3064 r/w cam11 least significant word register 0x 0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 104 - continued. register address r/w description reset value control registers (44) cam12m 0xfff0_3068 r/w cam12 most significant word register 0x0000_0000 cam12l 0xfff0_306c r/w cam12 least significant word register 0x 0000_0000 cam13m 0xfff0_3070 r/w cam13 most significant word register 0x0000_0000 cam13l 0xfff0_3074 r/w cam13 least significant word register 0x 0000_0000 cam14m 0xfff0_3078 r/w cam14 most significant word register 0x0000_0000 cam14l 0xfff0_307c r/w cam14 least significant word register 0x 0000_0000 cam15m 0xfff0_3080 r/w cam15 most significant word register 0x0000_0000 cam15l 0xfff0_3084 r/w cam15 least significant word register 0x 0000_0000 txdlsa 0xfff0_3088 r/w transmit descriptor link list start address register 0xffff_fffc rxdlsa 0xfff0_308c r/w receive descriptor link list start address register 0xffff_fffc mcmdr 0xfff0_3090 r/w mac command register 0x0000_0000 miid 0xfff0_3094 r/w mii management data register 0x0000_0000 miida 0xfff0_3098 r/w mii management control and address register 0x0090_0000 fftcr 0xfff0_309c r/w fifo thre shold control register 0x0000_0101 tsdr 0xfff0_30a0 w transmit star t demand register undefined rsdr 0xfff0_30a4 w receive star t demand register undefined dmarfc 0xfff0_30a8 r/w maximum receive frame control register 0x0000_0800 mien 0xfff0_30ac r/w mac inte rrupt enable register 0x0000_0000 status registers (11) mista 0xfff0_30b0 r/w mac inte rrupt status register 0x0000_0000 mgsta 0xfff0_30b4 r/w mac gener al status register 0x0000_0000 mpcnt 0xfff0_30b8 r/w missed pa cket count register 0x0000_7fff mrpc 0xfff0_30bc r mac receiv e pause count register 0x0000_0000 mrpcc 0xfff0_30c0 r mac receive pause current count register 0x0000_0000 mrepc 0xfff0_30c4 r mac remote pause count register 0x0000_0000 dmarfs 0xfff0_30c8 r/w dma receiv e frame status register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 105 - revision a2 continued. register address r/w description reset value status registers (11) ctxdsa 0xfff0_30cc r current transmit descriptor start address register 0x0000_0000 ctxbsa 0xfff0_30d0 r current transmit buffer start address register 0x0000_0000 crxdsa 0xfff0_30d4 r current receive descriptor start address register 0x0000_0000 crxbsa 0xfff0_30d8 r current receive buffer start address register 0x0000_0000 diagnostic registers (7) rxfsm 0xfff0_3200 r receive finite state machine register 0x0081_1101 txfsm 0xfff0_3204 r transmit finite state machine register 0x0101_1101 fsm0 0xfff0_3208 r finite stat e machine register 0 0x0001_0101 fsm1 0xfff0_320c r finite stat e machine register 1 0x1100_0100 dcr 0xfff0_3210 r/w debug configur ation register 0x0000_003f dmmir 0xfff0_3214 r debug mode mac information register 0x0000_0000 bistr 0xfff0_3300 r/w bist mode register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 106 - 6.5.2.1. register details cam command register (camcmr) the emc of W90N745 supports cam function fo r destination mac address recognition. the camcmr control the cam comparison functi on, and unicast, multicast, and broadcast packet reception. register address r/w description reset value camcmr 0xfff0_3000 r/w cam command register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ecmp ccam abp amp aup bits descriptions [31:5] reserved - [4] ecmp the ecmp(enable cam compare) controls the enable of cam comparison function for destination mac address recognition. if s/w wants to receive a packet with specific destination mac address, configures the mac addre ss into anyone of 16 cam entries, then enables that cam entry and set ecmp to 1. 1?b0: disable cam comparison f unction for destination mac address recognition. 1?b1: enable cam comparison func tion for destination mac address recognition. [3] ccam the ccam(complement cam compare) controls the complement of the cam comparison result. if t he ecmp and ccam are both enabled, the incoming packet with specific destination mac address configured in cam entry will be dropped. and the incoming packet with destination mac address doesn?t conf igured in any cam entry will be received. 1?b0: the cam comparison result doesn?t be complemented. 1?b1: the cam comparison result will be complemented. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 107 - revision a2 continued. bits descriptions [2] abp the accept broadcast packet controls the broadcast packet reception. if abp is enabled, emc receives all incoming packet it?s destination mac address is a broadcast address. 1?b0: emc receives packet depends on the cam comparison result. 1?b1: emc receives all broadcast packets. [1] amp the accept multicast packet controls the multicast packet reception. if amp is enabled, emc receives all incoming packet it?s destination mac address is a multicast address. 1?b0: emc receives packet depends on the cam comparison result. 1?b1: emc receives all multicast packets. [0] aup the accept unicast packet controls the unicast packet reception. if aup is enabled, emc receives all incoming packet it?s destination mac address is a unicast address. 1?b0: emc receives packet depends on the cam comparison result. 1?b1: emc receives all unicast packets. camcmr setting and comparison result camcmr setting and comparison result the following table is the address recognition resu lt in different camcmr configuration. the column result shows the incoming packet type t hat can pass the address recognition in specific cam configuration. the c, u, m and b represents the: c : it indicates the destination mac address of in coming packet has been configured in cam entry. u : it indicates the incoming packet is a unicast packet. m : it indicates the incoming packet is a multicast packet. b : it indicates the incoming packet is a broadcast packet. free datasheet http:///
W90N745cd/W90N745cdg - 108 - ecmp ccam aup amp abp result 0 0 0 0 0 no packet 0 0 0 0 1 b 0 0 0 1 0 m 0 0 0 1 1 m b 0 0 1 0 0 c u 0 0 1 0 1 c u b 0 0 1 1 0 c u m 0 0 1 1 1 c u m b 0 1 0 0 0 c u m b 0 1 0 0 1 c u m b 0 1 0 1 0 c u m b 0 1 0 1 1 c u m b 0 1 1 0 0 c u m b 0 1 1 0 1 c u m b 0 1 1 1 0 c u m b 0 1 1 1 1 c u m b 1 0 0 0 0 c 1 0 0 0 1 c b 1 0 0 1 0 c m 1 0 0 1 1 c n b 1 0 1 0 0 c u 1 0 1 0 1 c u b 1 0 1 1 0 c u m 1 0 1 1 1 c u m b 1 1 0 0 0 u m b 1 1 0 0 1 u m b 1 1 0 1 0 u m b 1 1 0 1 1 u m b 1 1 1 0 0 c u m b 1 1 1 0 1 c u m b 1 1 1 1 0 c u m b 1 1 1 1 1 c u m b free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 109 - revision a2 cam enable register (camen) the camen controls the validation of each cam entry. each cam entry must be enabled first before it can participate in the desti nation mac address recognition. register address r/w description reset value camen 0xfff0_3004 r/w cam enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 cam15en cam14en cam13en cam12en cam11en cam10en cam9en cam8en 7 6 5 4 3 2 1 0 cam7en cam6en cam5en cam4en cam3en cam2en cam1en cam0en bits descriptions [31:16] reserved [15:13] cam15en cam14en cam13en the cam entry 13, 14 and 15 are for pause control frame transmission. if s/w wants to trans mit a pause control frame out to network, the enable bits of these three cam entries all must be enabled first. [12] cam12en cam entry 12 is enabled 1?b0: cam entry 12 disabled. 1?b1: cam entry 12 enabled. [11] cam11en cam entry 11 is enabled 1?b0: cam entry 11 disabled. 1?b1: cam entry 11 enabled. [10] cam10en cam entry 10 is enabled 1?b0: cam entry 10 disabled. 1?b1: cam entry 10 enabled. free datasheet http:///
W90N745cd/W90N745cdg - 110 - continued. bits descriptions [9] cam9en cam entry 9 is enabled 1?b0: cam entry 9 disabled. 1?b1: cam entry 9 enabled. [8] cam8en cam entry 8 is enabled 1?b0: cam entry 8 disabled. 1?b1: cam entry 8 enabled. [7] cam7en cam entry 7 is enabled 1?b0: cam entry 7 disabled. 1?b1: cam entry 7 enabled. [6] cam6en cam entry 6 is enabled 1?b0: cam entry 6 disabled. 1?b1: cam entry 6 enabled. [5] cam5en cam entry 5 is enabled 1?b0: cam entry 5 disabled. 1?b1: cam entry 5 enabled. [4] cam4en cam entry 4 is enabled 1?b0: cam entry 4 disabled. 1?b1: cam entry 4 enabled. [3] cam3en cam entry 3 is enabled 1?b0: cam entry 3 disabled. 1?b1: cam entry 3 enabled. [2] cam2en cam entry 2 is enabled 1?b0: cam entry 2 disabled. 1?b1: cam entry 2 enabled. [1] cam1en cam entry 1 is enabled 1?b0: cam entry 1 disabled. 1?b1: cam entry 1 enabled. [0] cam0en cam entry 0 is enabled 1?b0: cam entry 0 disabled. 1?b1: cam entry 0 enabled. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 111 - revision a2 cam entry registers (camxx) register address r/w description reset value cam0m 0xfff0_3008 r/w cam0 most signi ficant word register 0x0000_0000 cam0l 0xfff0_300c r/w cam0 least significant word register 0x0000_0000 cam1m 0xfff0_3010 r/w cam1 most significant word register 0x0000_0000 cam1l 0xfff0_3014 r/w cam1 least significant word register 0x0000_0000 cam2m 0xfff0_3018 r/w cam2 most significant word register 0x0000_0000 cam2l 0xfff0_301c r/w cam2 least significant word register 0x0000_0000 cam3m 0xfff0_3020 r/w cam3 most significant word register 0x0000_0000 cam3l 0xfff0_3024 r/w cam3 least significant word register 0x0000_0000 cam4m 0xfff0_3028 r/w cam4 most significant word register 0x0000_0000 cam4l 0xfff0_302c r/w cam4 least significant word register 0x0000_0000 cam5m 0xfff0_3030 r/w cam5 most significant word register 0x0000_0000 cam5l 0xfff0_3034 r/w cam5 least significant word register 0x0000_0000 cam6m 0xfff0_3038 r/w cam6 most significant word register 0x0000_0000 cam6l 0xfff0_303c r/w cam6 least significant word register 0x0000_0000 cam7m 0xfff0_3040 r/w cam7 most significant word register 0x0000_0000 cam7l 0xfff0_3044 r/w cam7 least significant word register 0x0000_0000 cam8m 0xfff0_3048 r/w cam8 most significant word register 0x0000_0000 cam8l 0xfff0_304c r/w cam8 least significant word register 0x0000_0000 cam9m 0xfff0_3050 r/w cam9 most significant word register 0x0000_0000 cam9l 0xfff0_3054 r/w cam9 least significant word register 0x0000_0000 cam10m 0xfff0_3058 r/w cam10 most significant word register 0x0000_0000 cam10l 0xfff0_305c r/w cam10 least significant word register 0x0000_0000 cam11m 0xfff0_3060 r/w cam11 most significant word register 0x0000_0000 cam11l 0xfff0_3064 r/w cam11 least significant word register 0x0000_0000 cam12m 0xfff0_3068 r/w cam12 most significant word register 0x0000_0000 cam12l 0xfff0_306c r/w cam12 least significant word register 0x0000_0000 cam13m 0xfff0_3070 r/w cam13 most significant word register 0x0000_0000 cam13l 0xfff0_3074 r/w cam13 least significant word register 0x0000_0000 cam14m 0xfff0_3078 r/w cam14 most significant word register 0x0000_0000 cam14l 0xfff0_307c r/w cam14 least significant word register 0x0000_0000 cam15m 0xfff0_3080 r/w cam15 most significant word register 0x0000_0000 cam15l 0xfff0_3084 r/w cam15 least significant word register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 112 - camxm 31 30 29 28 27 26 25 24 mac address byte 5 (msb) 23 22 21 20 19 18 17 16 mac address byte 4 15 14 13 12 11 10 9 8 mac address byte 3 7 6 5 4 3 2 1 0 mac address byte 2 bits descriptions [31:0] camxm the camxm(camx most significant word) keeps the bit 47~16 of mac address. the x can be the 0~14. the register pair {camxm, camxl} represents a cam entry and can keep a mac address. for example, if the mac address 00- 50-ba-33-ba-44 is kept in cam entry 1, the register cam1 m is 32?h0050_ba33 and cam1l is 32?hba44_0000. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 113 - revision a2 camxl 31 30 29 28 27 26 25 24 mac address byte 1 23 22 21 20 19 18 17 16 mac address byte 0 (lsb) 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bits descriptions [31:16] camxl the camxl(camx least significant word) keeps the bit 15~0 of mac address. the x can be the 0~14. the register pair {camxm, camxl} represents a cam entry and can keep a mac address. for example, if the mac address 00- 50-ba-33-ba-44 is kept in cam entry 1, the register cam1 m is 32?h0050_ba33 and cam1l is 32?hba44_0000. [15:0] reserved - cam15m 31 30 29 28 27 26 25 24 length/type (msb) 23 22 21 20 19 18 17 16 length/type 15 14 13 12 11 10 9 8 op-code (msb) 7 6 5 4 3 2 1 0 op-code free datasheet http:///
W90N745cd/W90N745cdg - 114 - bits descriptions [31:0] length/type length/type field of pause control frame in the pause control frame, a length/type field is defined and will be 16?h8808. [15:0] op-code op code field of pause control frame in the pause control frame, an op code field is defined and will be 16?h0001. cam15l 31 30 29 28 27 26 25 24 operand (msb) 23 22 21 20 19 18 17 16 operand 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bits descriptions [31:16] operand pause parameter, in the pause control frame, an operand field is defined and controls how much ti me the destination ethernet mac controller is paused. the unit of t he operand is the slot time, the 512 bits time. [15:0] reserved free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 115 - revision a2 transmit descriptor link list start address register (txdlsa) the tx descriptor defined in emc is a link-list dat a structure. the txdlsa keeps the starting address of this link-list. in other words, the txdlsa keeps the starting address of the 1 st tx descriptor. s/w must configure txdlsa before enable bit txon of mcmdr register. register address r/w description reset value txdlsa 0xfff0_3088 r/w transmit descriptor link list start address register 0xffff_fffc 31 30 29 28 27 26 25 24 txdlsa 23 22 21 20 19 18 17 16 txdlsa 15 14 13 12 11 10 9 8 txdlsa 7 6 5 4 3 2 1 0 txdlsa bits descriptions [31:0] txdlsa the txdlsa(transmit descriptor link-list start address) keeps the start address of transmit descrip tor link-list. if the s/w enables the bit txon of mcmdr register, t he content of txdlsa will be loaded into the current transmit descripto r start address register (ctxdsa). the txdlsa doesn?t be updated by em c. during the operation, emc will ignore the bits [1:0] of tx dlsa. this means that each tx descriptor always must locate at word boundary memory address. receive descriptor link list st art address register (rxdlsa) the rx descriptor defined in emc is a link-list dat a structure. the rxdlsa keeps the starting address of this link-list. in other words, the rxdlsa keeps the starting address of the 1 st rx descriptor. s/w must configure rxdlsa before enable bit rxon of mcmdr register. register address r/w description reset value rxdlsa 0xfff0_308c r/w receive descriptor link list start address register 0xffff_fffc free datasheet http:///
W90N745cd/W90N745cdg - 116 - 31 30 29 28 27 26 25 24 rxdlsa 23 22 21 20 19 18 17 16 rxdlsa 15 14 13 12 11 10 9 8 rxdlsa 7 6 5 4 3 2 1 0 rxdlsa bits descriptions [31:0] rxdlsa the rxdlsa(receive descriptor link-list start address) keeps the start address of receive descrip tor link-list. if the s/w enables the bit rxon of mcmdr register, t he content of rxdlsa will be loaded into the current receive descriptor start address register (crxdsa). the rxdlsa doesn?t be updated by emc. during the operation, emc will ignore the bits [1:0] of rxdlsa. this means that each rx descriptor always must locate at word boundary memory address. mac command register (mcmdr) the mcmdr provides the control information fo r emc. some command settings affect both frame transmission and reception, such as bit fdup, the fu ll/half duplex mode selection, or bit opmod, the 100/10m bps mode selection. some command setti ngs control frame transmission and reception separately, likes bit txon and rxon. register address r/w description reset value mcmdr 0xfff0_3090 r/w mac command register 0x0000_0000 31 30 29 28 27 26 25 24 reserved swr 23 22 21 20 19 18 17 16 reserved lbk opmod enmdc fdup ensqe sdpz 15 14 13 12 11 10 9 8 reserved ndef txon 7 6 5 4 3 2 1 0 reserved spcrc aep acp arp alp rxon free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 117 - revision a2 bits descriptions [31:25] reserved - [24] swr the swr (software reset) implements a reset function to make the emc return default state. the swr is a self-clear bit. this means after the software reset finished, the swr will be cleared automatically. enable swr can also reset all control and status registers, except for opmo d bit of mcmdr register. the emc re-initial is needed after the software reset completed. 1?b0: software reset completed. 1?b1: enable software reset. [23:22] reserved - [21] lbk the lbk (internal loop back select) enables the emc operating on internal loop-back mode. if the lbk is enabled, the packet transmitted out will be loop-backed to rx. if the emc is operating on internal loop-back mode, it also means the emc is operating on full- duplex mode and the value of fdup of mcmdr register is ignored. beside, the lbk doesn?t be affected by swr bit. 1?b0: the emc operates in normal mode. 1?b1: the emc operates in internal loop-back mode. [20] opmod the operation mode select defines the emc is operating on 10m or 100m bps mode. the opmod doesn?t be affected by swr bit. 1?b0: the emc operates on 10mbps mode. 1?b1: the emc operates on 100mbps mode. [19] enmdc the enable mdc clock generation controls the mdc clock generation for mii management interface. if the enmdc is set to 1, the mdc clock generation is enabl ed. otherwise, the mdc clock generation is disabled. consequently , if s/w wants to access the registers of external phy thr ough mii management interface, the enmdc must be set to high. 1?b0: disable mdc clock generation. 1?b1: enable mdc clock generation. [18] fdup the full duplex mode select controls that emc is operating on full or half duplex mode. 1?b0: the emc operates on half duplex mode. 1?b1: the emc operates on full duplex mode. free datasheet http:///
W90N745cd/W90N745cdg - 118 - continued. bits descriptions [17] ensqe the enable sqe checking controls the enable of sqe checking. the sqe checking is only available while emc is operating on 10m bps and half duplex mode. in other words, the ensqe cannot affect emc operation, if the emc is oper ating on 100m bps or full duplex mode. 1?b0: disable sqe checking while emc is operating on 10mbps and half duplex mode. 1?b1: enable sqe checking while emc is operating on 10mbps and half duplex mode. [16] sdpz the send pause frame controls the pause control frame transmission. if s/w wants to send a pause control frame out, the cam entry 13, 14 and 15 must be configured first and the corresponding cam enable bit of camen register also must be set. then, set sdpz to 1 enables the pause control frame transmission. the sdpz is a self-clear bit. th is means after the pause control frame transmission has completed, the sdpz will be cleared automatically. it is recommended that only enables spdz while emc is operating on full duplex mode. 1?b0: the pause control frame transmission has completed. 1?b1: enable emc to transmit a pause control frame out. [15:10] reserved - [9] ndef the no defer controls the enable of deferral exceed counter. if ndef is set to high, the deferral exceed counter is disabled. the ndef is only useful while emc is operating on half duplex mode. 1?b0: the deferral exceed counter is enabled. 1?b1: the deferral exceed counter is disabled. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 119 - revision a2 continued. bits descriptions [8] txon the frame transmission on controls the normal packet transmission of emc. if the txon is set to high, the emc starts the packet transmission process, including the tx descriptor fetching, packet transmission and tx descriptor modification. it is must to finish emc initial sequence before enable txon. otherwise, the emc operation is undefined. if the txon is disabled during em c is transmitting a packet out, the emc stops the packet transmission process after the current packet transmission finished. 1?b0: the emc stops packet transmission process. 1?b1: the emc starts packet transmission process. [7:6] reserved - [5] spcrc the strip crc checksum controls if the length of incoming packet is calculated with 4 bytes crc checksum. if the spcrc is set to high, 4 bytes crc checksum is excluded from length calculation of incoming packet. 1?b0: the 4 bytes crc checksum is included in packet length calculation. 1?b1: the 4 bytes crc checksum is excluded in packet length calculation. [4] aep the accept crc error packet controls the emc accepts or drops the crc error packet. if the aep is set to high, the incoming packet with crc error will be received by emc as a good packet. 1?b0: the crc error packet will be dropped by emc. 1?b1: the crc error packet will be accepted by emc. [3] acp the accept control packet controls the control frame reception. if the acp is set to high, the emc will a ccept the control frame. otherwise, the control frame will be dropped. it is recommended that s/w only enable aep while emc is operating on full duplex mode. 1?b0: the control frame will be dropped by emc. 1?b1: the control frame will be accepted by emc. free datasheet http:///
W90N745cd/W90N745cdg - 120 - continued. bits descriptions [2] arp the accept runt packet controls t he runt packet, which length is less than 64 bytes, reception. if the arp is set to high, the emc will accept the runt packet. otherwise, the runt packet will be dropped. 1?b0: the runt packet will be dropped by emc. 1?b1: the runt packet will be accepted by emc. [1] alp the accept long packet controls the long packet, which packet length is greater than 1518 bytes, rec eption. if the alp is set to high, the emc will accept the long packet. otherwise, the long packet will be dropped. 1?b0: the long packet will be dropped by emc. 1?b1: the long packet will be accepted by emc. [0] rxon the frame reception on controls the normal packet reception of emc. if the rxon is set to high, the emc starts the packet reception process, including the rx descrip tor fetching, packet reception and rx descriptor modification. it is must to finish emc initial sequence before enable rxon. otherwise, the emc operation is undefined. if the rxon is disabled during emc is receiving an incoming packet, the emc stops the packet reception process after the current packet reception finished. 1?b0: the emc stops packet reception process. 1?b1: the emc starts packet reception process. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 121 - revision a2 mii management data register (miid) the emc provides mii management function to access t he control and status regi sters of the external phy. the miid register is used to store the data that will be written into the registers of external phy for write command or the data that is read from the registers of external phy for read command. register address r/w description reset value miid 0xfff0_3094 r/w mii management data register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 miidata 7 6 5 4 3 2 1 0 miidata bits descriptions [31:16] reserved - [15:0] miidata the mii management data is the 16 bits data that will be written into the registers of external phy for mii management write command or the data from the registers of external phy for mii management read command. free datasheet http:///
W90N745cd/W90N745cdg - 122 - mii management control and address register (miida) the emc provides mii management function to access t he control and status regi sters of the external phy. the miida register is used to keep the m ii management command information, like the register address, external phy address, m dc clocking rate, read/write etc. register address r/w description reset value miida 0xfff0_3098 r/w mii management control and address register 0x0090_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 mdccr mdcon presp busy write 15 14 13 12 11 10 9 8 reserved phyad 7 6 5 4 3 2 1 0 reserved phyrad bits descriptions [31:24] reserved - [23:20] mdccr the mdc clock rating controls the mdc clock rating for mii management i/f. depend on the ieee std. 802.3 cl ause 22.2.2.11, the minimum period for mdc shall be 400ns. in other words, the maximum frequency for mdc is 2.5mhz. the mdc is divided from the ahb bus clock, the hclk. consequently, for different hclks the different ratios are required to generate appropriate mdc clock. the following table shows relationship between hclk and mdc clock in different mdccr configurations. the t hclk indicates the period of hclk. [19] mdc the mdc clock on always controls the mdc clock generation. if the mdcon is set to high, the mdc clock actives always. otherwise, the mdc will only active while s/w issues a mii management command. 1?b0: the mdc clock will only active while s/w issues a mii management command. 1?b1: the mdc clock actives always. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 123 - revision a2 continued. bits descriptions [18] presp the preamble suppress controls the preamble field generation of mii management frame. if the presp is set to high, the preamble field generation of mii management frame is skipped. 1?b0: preamble field generation of mii management frame is not skipped. 1?b1: preamble field generation of mii management frame is skipped. [17] busy the busy bit controls the enable of the mii management frame generation. if s/w wants to access regi sters of external phy, it set busy to high and emc generates the mii management frame to external phy through mii management i/f. the busy is a self-clear bit. th is means the busy will be cleared automatically after the mii management command finished. 1?b0: the mii management has finished. 1?b1: enable emc to generate a mii management command to external phy. [16] write the write command defines the mii management command is a read or write. 1?b0: the mii management command is a read command. 1?b1: the mii management command is a write command. [15:13] reserved [12:8] phyad the phy address keeps the address to differentiate which external phy is the target of the mii management command. [7:5] reserved - [4:0] phyrad the phy register address keeps the address to indicate which register of external phy is the target of the mii management command. free datasheet http:///
W90N745cd/W90N745cdg - 124 - mdccr [23:20] mdc clock period mdc clock frequency 4?b0000 4 x t hclk hclk/4 4?b0001 6 x t hclk hclk/6 4?b0010 8 x t hclk hclk/8 4?b0011 12 x t hclk hclk/12 4?b0100 16 x t hclk hclk/16 4?b0101 20 x t hclk hclk/20 4?b0110 24 x t hclk hclk/24 4?b0111 28 x t hclk hclk/28 4?b1000 30 x t hclk hclk/30 4?b1001 32 x t hclk hclk/32 4?b1010 36 x t hclk hclk/36 4?b1011 40 x t hclk hclk/40 4?b1100 44 x t hclk hclk/44 4?b1101 48 x t hclk hclk/48 4?b1110 54 x t hclk hclk/54 4?b1111 60 x t hclk hclk/60 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 125 - revision a2 mii management function frame format in ieee std. 802.3 clause 22.2.4, the mii m anagement function is defined. the mii management function is used for the purpose of controlling the phy and gathering status from the phy. the mii management frame format is shown as follow. management frame fields pre st op phyad regad ta data idle read 1?1 01 10 aaaaa rrrrr z0 dddddddddddddddd z write 1?1 01 01 aaaaa rrrrr 10 dddddddddddddddd z mii management function configure sequence read write 1. set appropriate mdccr. 2. set phyad and phyrad. 3. set write to 1?b0 4. set bit busy to 1?b1 to send a mii management frame out. 5. wait busy to become 1?b0. 6. read data from miid register. 7. finish the read command. 1. write data to miid register 2. set appropriate mdccr. 3. set phyad and phyrad. 4. set write to 1?b1 5. set bit busy to 1?b1 to send a mii management frame out. 6. wait busy to become 1?b0. 7. finish the write command. free datasheet http:///
W90N745cd/W90N745cdg - 126 - fifo threshold control register (fftcr) the fftcr defines the high and low threshold of in ternal fifos, including txfifo and rxfifo. the threshold of internal fifos is related to emc request generation and when the frame transmission starts. the fftcr also defines the burst length of ahb bus cycle for system memory access. register address r/w description reset value fftcr 0xfff0_309c r/w fifo threshold control register 0x0000_0101 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved blength reserved 15 14 13 12 11 10 9 8 reserved txthd 7 6 5 4 3 2 1 0 reserved rxthd bits descriptions [31:22] reserved - [21:20] blength the dma burst length defines the burst length of ahb bus cycle while emc accesses system memory. 2?b00: 4 words 2?b01: 8 words 2?b10: 16 words 2?b11: 16 words [19:10] reserved - free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 127 - revision a2 continued. bits descriptions [9:8] txthd the txfifo low threshold controls when txdma requests internal arbiter for data transfer between system memory and txfifo. the txthd defines not only the low thres hold of txfifo, but also the high threshold. the high threshold is t he twice of low threshold always. during the packet transmission, if the txfifo reaches the high threshold, the txdma stops generat e request to transfer frame data from system memory to txfifo. if the frame data in txfifo is less than low threshold, txdma starts to transfer frame data from system memory to txfifo. the txthd also defines when the tx mac starts to transmit frame out to network. the txmac starts to transmit the frame out while the txfifo first time reaches the high threshold during the transmission of the frame. if the frame data length is less than txfifo high threshold, the txmac starts to tr ansmit the frame out after the frame data are all inside the txfifo. 2?b00: undefined. 2?b01: txfifo low threshold is 64b and high threshold is 128b. 2?b10: txfifo low threshold is 80b and high threshold is 160b. 2?b11: txfifo low threshold is 96b and high threshold is 192b. [7:2] reserved [1:0] rxthd the rxfifo high threshold controls when rxdma requests internal arbiter for data transfer between rxfifo and system memory. the rxthd defines not only the high thres hold of rxfifo, but also the low threshold. the low threshold is the half of high threshold always. during the packet reception, if the rxfifo reaches the high threshold, the rxdma starts to transfer fram e data from rxfifo to system memory. if the frame data in rxfi fo is less than low threshold, rxdma stops to transfer the frame data to system memory. 2?b00: depend on the burst length se tting. if the burst length is 8 words, high threshold is 8 words, too. 2?b01: rxfifo high threshold is 64b and low threshold is 32b. 2?b10: rxfifo high threshold is 128b and low threshold is 64b. 2?b11: rxfifo high threshold is 192b and low threshold is 96b. free datasheet http:///
W90N745cd/W90N745cdg - 128 - transmit start demand register (tsdr) if the tx descriptor is not available for use of tx dma after the txon of mcmdr register is enabled, the fsm (finite state machine) of txdma enters t he halt state and the frame transmission is halted. after the s/w has prepared the new tx descriptor for frame transmission, it must issue a write command to tsdr register to make txdma leave halt state and contiguous frame transmission. the tsdr is a write only register and read from this regi ster is undefined. the writ e to tsdr register has took effect only while txdm a stayed at halt state. register address r/w description reset value tsdr 0xfff0_30a0 w transmit start demand register undefined bits descriptions [31:0] reserved - receive start demand register (rsdr) if the rx descriptor is not available for use of rx dma after the rxon of mcmdr register is enabled, the fsm (finite state machine) of rxdma enters the halt state and the frame reception is halted. after the s/w has prepared the new rx descriptor for frame reception, it must issue a write command to rsdr register to make rxdma leave halt st ate and contiguous frame reception. the rsdr is a write only register and read from this register is undef ined. the write to rsdr r egister has took effect only while rxdma stayed at halt state. register address r/w description reset value rsdr 0xfff0_30a4 w receive start demand register undefined bits descriptions [31:0] reserved -- free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 129 - revision a2 maximum receive frame cont rol register (dmarfc) the dmarfc defines the maximum frame length fo r a received frame that can be stored in the system memory. it is recommend that only use this r egister while s/w wants to receive a frame which length is greater than 1518 bytes. register address r/w description reset value dmarfc 0xfff0_30a8 r/w maximum receive frame control register 0x0000_0800 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rxms 7 6 5 4 3 2 1 0 rxms bits descriptions [31:16] reserved - [15:0] rxms the maximum receive frame length defines the maximum frame length for received frame. if the frame length of received frame is greater than rxms, and bit endfo of mien register is also enabled, the bit dfoi of mista register is set and the rx interrupt is triggered. it is recommended that only use rxms to qualify the length of received frame while s/w wants to receive a frame which length is greater than 1518 bytes. free datasheet http:///
W90N745cd/W90N745cdg - 130 - mac interrupt enable register (mien) the mien controls the enable of emc interrupt stat us to generate interrupt. two interrupts, rxintr for frame reception and txintr for frame tr ansmission, are generated from emc to cpu. register address r/w description reset value mien 0xfff0_30ac r/w mac interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved entxberr 23 22 21 20 19 18 17 16 entdu enlc entxabt enncs enexdef entxcp entxemp entxintr 15 14 13 12 11 10 9 8 reserved encfr reserved enrxberr enrdu enden endfo 7 6 5 4 3 2 1 0 enmmp enrp enalie enrxgd enptle enrxov encrce enrxintr bits descriptions [31:25] reserved - [24] entxberr the enable transmit bus error interrupt controls the txberr interrupt generation. if txberr of mista register is set, and both entxberr and entxintr are enabled, the emc generates the tx interrupt to cpu. if entxberr or entx intr is disabled, no tx interrupt is generated to cpu even the txbe rr of mista register is set. 1?b0: txberr of mista register is masked from tx interrupt generation. 1?b1: txberr of mista register can participate in tx interrupt generation. [23] entdu the enable transmit descriptor unavailable interrupt controls the tdu interrupt generation. if tdu of mista register is set, and both entdu and entxintr are enabled, the emc generates the tx interrupt to cpu. if entdu or entxin tr is disabled, no tx interrupt is generated to cpu even the tdu of mista register is set. 1?b0: tdu of mista register is ma sked from tx interrupt generation. 1?b1: tdu of mista register can par ticipate in tx interrupt generation. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 131 - revision a2 continued bits descriptions [22] enlc the enable late collision interrupt controls the lc interrupt generation. if lc of mista register is set, and both enlc and entxintr are enabled, the emc generates the tx interrupt to cpu. if enlc or entxintr is disabled, no tx interrupt is generated to cpu even the lc of mista register is set. 1?b0: lc of mista register is ma sked from tx interrupt generation. 1?b1: lc of mista register can par ticipate in tx interrupt generation. [21] entxabt the enable transmit abort interrupt controls the txabt interrupt generation. if txabt of mista register is set, and both entxabt and entxintr are enabled, the emc generates the tx interrupt to cpu. if entxabt or entxintr is disabled, no tx interrupt is generated to cpu even the txabt of mista register is set. 1?b0: txabt of mista register is masked from tx interrupt generation. 1?b1: txabt of mista register can participate in tx interrupt generation. [20] enncs the enable no carrier sense interrupt controls the ncs interrupt generation. if ncs of mista regi ster is set, and both enncs and entxintr are enabled, the emc generates the tx interrupt to cpu. if enncs or entxintr is disabled, no tx interrupt is generated to cpu even the ncs of mista register is set. 1?b0: ncs of mista register is ma sked from tx interrupt generation. 1?b1: ncs of mista register can par ticipate in tx interrupt generation. [19] enexdef the enable defer exceed interrupt controls the exdef interrupt generation. if exdef of mista register is set, and both enexdef and entxintr are enabled, the emc generates the tx interrupt to cpu. if enexdef or entxintr is disabled, no tx interrupt is generated to cpu even the exdef of mista register is set. 1?b0: exdef of mista register is masked from tx interrupt generation. 1?b1: exdef of mista register can participate in tx interrupt generation. [18] entxcp the enable transmit completion interrupt controls the txcp interrupt generation. if txcp of mista register is set, and both entxcp and entxintr are enabled, the emc generates the tx interrupt to cpu. if entxcp or entx intr is disabled, no tx interrupt is generated to cpu even the txcp of mista register is set. 1?b0: txcp of mista register is masked from tx interrupt generation. 1?b1: txcp of mista register can participate in tx interrupt generation. free datasheet http:///
W90N745cd/W90N745cdg - 132 - continued. bits descriptions [17] entxemp the enable transmit fifo underflow interrupt controls the txemp interrupt generation. if txemp of mista register is set, and both entxemp and entxintr are enabled, the emc generates the tx interrupt to cpu. if entxemp or entx intr is disabled, no tx interrupt is generated to cpu even the txemp of mista register is set. 1?b0: txemp of mista register is masked from tx interrupt generation. 1?b1: txemp of mista register can participate in tx interrupt generation. [16] entxintr the entxintr controls the tx interrupt generation. if enable transmit interrupt is enabled and txintr of mista register is high, emc generates the tx interrupt to cpu. if entxintr is disabled, no tx interrupt is gener ated to cpu even the status bits 17~24 of mista are set and the corresponding bits of mien are enabled. in other words, if s/w want s to receive tx interrupt from emc, this bit must be enabled. and, if s/w doesn?t want to receive any tx interrupt from emc, disables this bit. 1?b0: txintr of mista register is masked and tx interrupt generation is disabled. 1?b1: txintr of mista register is unmasked and tx interrupt generation is enabled. [15] reserved -- [14] encfr the enable control frame receive interrupt controls the cfr interrupt generation. if cfr of mista register is set, and both encfr and entxintr are enabled, the emc generates the rx interrupt to cpu. if encfr or entxintr is di sabled, no rx interrupt is generated to cpu even the cfr of mista register is set. 1?b0: cfr of mista register is ma sked from rx interrupt generation. 1?b1: cfr of mista register can par ticipate in rx interrupt generation. [13:12] reserved -- [11] enrxberr the enable receive bus error interrupt controls the rxberr interrupt generation. if rxberr of mista regi ster is set, and both enrxberr and entxintr are enabled, the emc generates the rx interrupt to cpu. if enrxberr or entxintr is disabled, no rx interrupt is generated to cpu even the rxberr of mista register is set. 1?b0: rxberr of mista register is masked from rx interrupt generation. 1?b1: rxberr of mista register can participate in rx interrupt generation. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 133 - revision a2 continued. bits descriptions [10] enrdu the enable receive descriptor unavailable interrupt controls the rdu interrupt generation. if rdu of mista register is set, and both enrdu and entxintr are enabled, the emc generates the rx interrupt to cpu. if enrdu or entxintr is disabled, no rx interrupt is generated to cpu even the rdu of mista register is set. 1?b0: rdu of mista register is ma sked from rx interrupt generation. 1?b1: rdu of mista register can par ticipate in rx interrupt generation. [9] enden the enable dma early notification interrupt controls the deni interrupt generation. if deni of mi sta register is set, and both enden and entxintr are enabled, the emc generates the rx interrupt to cpu. if enden or entxintr is di sabled, no rx interrupt is generated to cpu even the deni of mista register is set. 1?b0: deni of mista register is masked from rx interrupt generation. 1?b1: deni of mista register can participate in rx interrupt generation. [8] endfo the enable maximum frame length interrupt controls the dfoi interrupt generation. if dfoi of mista register is set, and both endfo and entxintr are enabled, the emc generates the rx interrupt to cpu. if endfo or entxintr is di sabled, no rx interrupt is generated to cpu even the dfoi of mista register is set. 1?b0: dfoi of mista register is masked from rx interrupt generation. 1?b1: dfoi of mista register can participate in rx interrupt generation. [7] enmmp the enable more missed packet interrupt controls the mmp interrupt generation. if mmp of mista register is set, and both enmmp and entxintr are enabled, the emc generates the rx interrupt to cpu. if enmmp or entxintr is disabled, no rx interrupt is generated to cpu even the mmp of mista register is set. 1?b0: mmp of mista register is ma sked from rx interrupt generation. 1?b1: mmp of mista register can par ticipate in rx interrupt generation. [6] enrp the enable runt packet interrupt controls the rp interrupt generation. if rp of mista register is set, and both enrp and entxintr are enabled, the emc generates the rx interrupt to cpu. if enrp or entxintr is disabled, no rx interrupt is generated to cpu even the rp of mista register is set. 1?b0: rp of mista register is ma sked from rx interrupt generation. 1?b1: rp of mista register can par ticipate in rx interrupt generation. free datasheet http:///
W90N745cd/W90N745cdg - 134 - continued. bits descriptions [5] enalie the enable alignment error interrupt controls the alie interrupt generation. if alie of mista register is set, and both enalie and entxintr are enabled, the emc generates the rx interrupt to cpu. if enalie or entxintr is disabled, no rx interrupt is generated to cpu even the alie of mista register is set. 1?b0: alie of mista register is masked from rx interrupt generation. 1?b1: alie of mista register can participate in rx interrupt generation. [4] enrxgd the enable receive good interrupt controls the rxgd interrupt generation. if rxgd of mista regi ster is set, and both enrxgd and entxintr are enabled, the emc generates the rx interrupt to cpu. if enrxgd or entxintr is disabled, no rx interrupt is generated to cpu even the rxgd of mista register is set. 1?b0: rxgd of mista register is masked from rx interrupt generation. 1?b1: rxgd of mista register can participate in rx interrupt generation. [3] enptle the enable packet too long interrupt controls the ptle interrupt generation. if ptle of mista register is set, and both enptle and entxintr are enabled, the emc generates the rx interrupt to cpu. if enptle or entxintr is disabled, no rx interrupt is generated to cpu even the ptle of mista register is set. 1?b0: ptle of mista register is masked from rx interrupt generation. 1?b1: ptle of mista register can participate in rx interrupt generation. [2] enrxov the enable receive fifo overflow interrupt controls the rxov interrupt generation. if rxov of mista register is set, and both enrxov and entxintr are enabled, the emc generates the rx interrupt to cpu. if enrxov or entx intr is disabled, no rx interrupt is generated to cpu even the rxov of mista register is set. 1?b0: rxov of mista register is masked from rx interrupt generation. 1?b1: rxov of mista register can participate in rx interrupt generation. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 135 - revision a2 continued. bits descriptions [1] encrce the enable crc error interrupt controls the crce interrupt generation. if crce of mista regi ster is set, and both encrce and entxintr are enabled, the emc generates the rx interrupt to cpu. if encrce or entxintr is disabled, no rx interrupt is generated to cpu even the crce of mista register is set. 1?b0: crce of mista register is masked from rx interrupt generation. 1?b1: crce of mista register c an participate in rx interrupt generation. [0] enrxintr the enable receive interrupt controls the rx interrupt generation. if enrxintr is enabled and rxintr of mista register is high, emc generates the rx interrupt to cpu. if enrxintr is disabled, no rx interrupt is generated to cpu even t he status bits 1~14 of mista are set and the corresponding bits of mien are enabled. in other words, if s/w wants to receive rx interrupt from emc, this bit must be enabled. and, if s/w doesn?t want to rece ive any rx interrupt from emc, disables this bit. 1?b0: rxintr of mista register is masked and rx interrupt generation is disabled. 1?b1: rxintr of mista register is unmasked and rx interrupt generation is enabled. free datasheet http:///
W90N745cd/W90N745cdg - 136 - mac interrupt status register (mista) the mista keeps much emc statuses, like frame transmission and reception status, internal fifo status and also nata processing st atus. the statuses kept in mist a will trigger the reception or transmission interrupt. the mista is a write clear register and write 1 to corresponding bit clears the status and also clears the interrupt. register address r/w description reset value mista 0xfff0_30b0 r/w mac interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved txberr 23 22 21 20 19 18 17 16 tdu lc txabt ncs exdef txcp txemp txintr 15 14 13 12 11 10 9 8 reserved cfr reserved rxberr rdu deni dfoi 7 6 5 4 3 2 1 0 mmp rp alie rxgd p tle rxov crce rxintr bits descriptions [31:25] reserved - [24] txberr the transmit bus error interrupt high indicates the memory controller replies error res ponse while emc access system memory through txdma during packet transmission process. reset emc is recommended while txberr status is high. if the txberr is high and entxberr of mien register is enabled, the txintr will be high. write 1 to this bit clears the txberr status. 1?b0: no error response is received. 1?b1: error response is received. [23] tdu the transmit descriptor unavailable interrupt high indicates that there is no available tx descriptor for packet transmission and txdma will stay at halt state. once, the txdma enters the halt state, s/w must issues a write command to tsdr register to make txdma leave halt state while new tx descriptor is available. if the tdu is high and entdu of mien register is enabled, the txintr will be high. write 1 to this bit clears the tdu status. 1?b0: tx descriptor is available. 1?b1: tx descriptor is unavailable. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 137 - revision a2 continued. bits descriptions [22] lc the late collision interrupt high indicates the collision occurred in the outside of 64 bytes collision window. th is means after the 64 bytes of a frame has transmitted out to the net work, the collision still occurred. the late collision check will only be done while emc is operating on half-duplex mode. if the lc is high and enlc of mien register is enabled, the txintr will be high. write 1 to this bit clears the lc status. 1?b0: no collision occurred in the outside of 64 bytes collision window. 1?b1: collision occurred in the outside of 64 bytes collision window. [21] txabt the transmit abort interrupt high indicates the packet incurred 16 consecutive collisions during tr ansmission, and then the transmission process for this packet is aborted. the transmission abort is only available while emc is operating on half-duplex mode. if the txabt is high and entxabt of mien register is enabled, the txintr will be high. write 1 to this bit clears the txabt status. 1?b0: packet doesn?t incur 16 consecutive collisions during transmission. 1?b1: packet incurred 16 consecutiv e collisions during transmission. [20] ncs the no carrier sense interrupt high indicates the mii i/f signal crs doesn?t active at the start of or during the packet transmission. the ncs is only available while emc is operating on half-duplex mode. if the ncs is high and enncs of mien register is enabled, the txintr will be high. write 1 to this bit clears the ncs status. 1?b0: crs signal actives correctly. 1?b1: crs signal doesn?t active at the start of or during the packet transmission. [19] exdef the defer exceed interrupt high indicates the frame waiting for transmission has deferred over 0.32768ms on 100mbps mode, or 3.2768ms on 10mbps mode. the deferral exceed check will only be done while bit ndef of mcmdr is disabled, and emc is operating on half-duplex mode. if the exdef is high and enexdef of mien register is enabled, the txintr will be high. write 1 to th is bit clears the exdef status. 1?b0: frame waiting for transmissi on has not deferred over 0.32768ms (100mbps) or 3.2768ms (10mbps). 1?b1: frame waiting for transmi ssion has deferred over 0.32768ms (100mbps) or 3.2768ms (10mbps). free datasheet http:///
W90N745cd/W90N745cdg - 138 - continued. bits descriptions [18] txcp the transmit completion interrupt indicates the packet transmission has completed correctly. if the txcp is high and entxcp of mien register is enabled, the txintr will be high. write 1 to this bit clears the txcp status. 1?b0: the packet transmission doesn?t complete. 1?b1: the packet transmission has completed. [17] txemp the transmit fifo underflow interrupt high indicates the txfifo underflow occurred during packet transmission. while the txfifo underflow occurred, the emc will retransmit the packet automatically without s/w interv ention. if the txfifo underflow occurred often, it is recommended that modify txfifo threshold control, the txthd of fftcr register, to higher level. if the txemp is high and entxemp of mien register is enabled, the txintr will be high. write 1 to this bit clears the txemp status. 1?b0: no txfifo underflow occurred during packet transmission. 1?b0: txfifo underflow occurred during packet transmission. [16] txintr the transmit interrupt indicates the tx interrupt status. if txintr high and its corresponding enable bit, entxintr of mista register, is also high indicates the emc generates tx interrupt to cpu. if txintr is high but entxintr of mista is disabled, no tx interrupt is generated. the txintr is logic or result of the bits 17~24 in mista register do logic and with the corresponding bits in mien register. in other words, if one of the bits 17~24 in mista register is high and its corresponding enable bit in mien register is also enabled, the txintr will be high. because the txintr is a logic or result, clears bits 17~24 of mista regi ster makes txintr be cleared, too. 1?b0: no status of bits 17~24 in mista is set or no enable of bits 17~24 in mien is turned on. 1?b1: at least one status of bits 17~24 in mista is set and its corresponding enable bit is turned on. [15] reserved free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 139 - revision a2 continued. bits descriptions [14] cfr the control frame receive interrupt high indicates emc receives a flow control frame. the cfr only available while emc is operating on full duplex mode. if the cfr is high and encfr of mien register is enabled, the rxintr will be high. write 1 to this bit clears the cfr status. 1?b0: the emc doesn?t receive the flow control frame. 1?b1: the emc receives a flow control frame. [13:12] reserved [11] rxberr the receive bus error interrupt high indicates the memory controller replies error res ponse while emc access system memory through rxdma during packet reception process. reset emc is recommended while rxberr status is high. if the rxberr is high and enrxberr of mien register is enabled, the rxintr will be high. write 1 to this bit clears the rxberr status. 1?b0: no error response is received. 1?b1: error response is received. [10] rdu the receive descriptor unavailabl e interrupt high indicates that there is no available rx descriptor for packet reception and rxdma will stay at halt state. once, the rxdma enters the halt state, s/w must issues a writ e command to rsdr register to make rxdma leave halt state while new rx descriptor is available. if the rdu is high and enrdu of mien register is enabled, the rxintr will be high. write 1 to this bit clears the rdu status. 1?b0: rx descriptor is available. 1?b1: rx descriptor is unavailable. [9] deni the dma early notification interrupt high indicates the emc has received the length/type field of the incoming packet. if the deni is high and endeni of mien register is enabled, the rxintr will be high. write 1 to this bit clears the deni status. 1?b0: the length/type field of in coming packet has not received yet. 1?b1: the length/type field of incoming packet has received. free datasheet http:///
W90N745cd/W90N745cdg - 140 - continued. bits descriptions [8] dfoi the maximum frame length interrupt high indicates the length of the incoming packet has exceeded the length limitation configured in dmarfc register and the incoming packet is dropped. if the dfoi is high and endfo of mien register is enabled, the rxintr will be high. write 1 to this bit clears the dfoi status. 1?b0: the length of the incomi ng packet doesn?t exceed the length limitation configured in dmarfc. 1?b1: the length of the incomi ng packet has exceeded the length limitation configured in dmarfc. [7] mmp the more missed packet interrupt high indicates the mpcnt, missed packet count, has overflow. if the mmp is high and enmmp of mien register is enabled, the rxintr will be high. write 1 to this bit clears the mmp status. 1?b0: the mpcnt has not rolled over yet. 1?b1: the mpcnt has rolled over yet. [6] rp runt packet interrupt the rp high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped. if the arp of mcmdr register is set, the short packet is regarded as a good packet and rp will not be set. if the rp is high and enrp of mien register is enabled, the rxintr will be high. write 1 to this bit clears the rp status. 1?b0: the incoming frame is not a short frame or s/w wants to receive a short frame. 1?b1: the incoming frame is a short frame and dropped. [5] alie the alignment error interrupt hi gh indicates the length of the incoming frame is not a multiple of byte. if the alie is high and enalie of mien register is enabled, the rxintr will be high. write 1 to th is bit clears the alie status. 1?b0: the frame length is a multiple of byte. 1?b1: the frame length is not a multiple of byte. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 141 - revision a2 continued. bits descriptions [4] rxgd the receive good interrupt high indicates the frame reception has completed. if the rxgd is high and enrxgd of mien register is enabled, the rxintr will be high. write 1 to this bit clears the rxgd status. 1?b0: the frame reception has not complete yet. 1?b1: the frame reception has completed. [3] ptle the packet too long interrupt high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped. if the alp of mcmdr register is set, the long packet will be regarded as a good packet and ptle will not be set. if the ptle is high and enptle of mien register is enabled, the rxintr will be high. write 1 to this bit clears the ptle status. 1?b0: the incoming frame is not a long frame or s/w wants to receive a long frame. 1?b1: the incoming frame is a long frame and dropped. [2] rxov the receive fifo overflow interrupt high indicates the rxfifo overflow occurred during packet reception. while the rxfifo overflow occurred, the emc drops the current receiving packer. if the rxfifo overflow occurred often, it is recommended that modify rxfifo threshold contro l, the rxthd of fftcr register, to higher level. if the rxov is high and enrxov of mien register is enabled, the rxintr will be high. write 1 to this bit clears the rxov status. 1?b0: no rxfifo overflow o ccurred during packet reception. 1?b0: rxfifo overflow occu rred during packet reception. [1] crce the crc error interrupt high indicates the incoming packet incurred the crc error and the packet is dropped. if the aep of mcmdr register is set, the crc error packet will be regarded as a good packet and crce will not be set. if the crce is high and encrce of mien register is enabled, the rxintr will be high. write 1 to this bit clears the crce status. 1?b0: the frame doesn?t incur crc error. 1?b1: the frame incurred crc error. free datasheet http:///
W90N745cd/W90N745cdg - 142 - continued. bits descriptions [0] rxintr the receive interrupt indicates the rx interrupt status. if rxintr high and its corresponding enable bit, enrxintr of mista register, is also high indicates the emc generates rx interrupt to cpu. if rxintr is high but enrxintr of mista is disabled, no rx interrupt is generated. the rxintr is logic or result of the bits 1~14 in mista register do logic and with the corresponding bits in mien register. in other words, if one of the bits 1~14 in mista register is high and its corresponding enable bit in mien register is also enabled, the rxintr will be high. because the rxintr is a logic or result, clears bits 1~14 of mista register makes rxintr be cleared, too. 1?b0: no status of bits 1~14 in mista is set or no enable of bits 1~14 in mien is turned on. 1?b1: at least one status of bits 1~14 in mista is set and its corresponding enable bit is turned on. mac general status register (mgsta) the mgsta also keeps the statuses of emc. but the statuses in the mgsta will not trigger any interrupt. the mgsta is a write clear register and write 1 to corresponding bit clears the status. register address r/w description reset value mgsta 0xfff0_30b4 r/w mac general status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved txha sqe pau def 7 6 5 4 3 2 1 0 ccnt reserved rffull rxha cfr free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 143 - revision a2 bits descriptions [31:12] reserved - [11] txha the transmission halted high indicates the next normal packet transmission process will be halted because the bit tx on of mcmdr is disabled be s/w. 1?b0: next normal packet transmission process will go on. 1?b1: next normal packet transmission process will be halted. [10] sqe the signal quality error high indicate s the sqe error found at end of packet transmission on 10mbps half-duplex mode. the sqe error check will only be done while both bit ensqe of mcmdr is enabled and emc is operating on 10mbps half-duplex mode. 1?b0: no sqe error found at end of packet transmission. 1?b0: sqe error found at end of packet transmission. [9] pau the transmission paused high indicates the next normal packet transmission process will be paused temporally because emc received a pause control frame, or s/w set bit sdpz of mcmdr and make emc to transmit a pause control frame out. 1?b0: next normal packet transmission process will go on. 1?b1: next normal packet transmission process will be paused. [8] def the deferred transmission high indicates the packet transmission has deferred once. the def is only available while emc is operating on half- duplex mode. 1?b0: packet transmission doesn?t defer. 1?b1: packet transmission has deferred once. [7:4] ccnt the collision count indicates the how many collision occurred consecutively during a packet transmission. if the packe t incurred 16 consecutive collisions during transmission, the ccnt will be 4?h0 and bit txabt will be set to 1. [3] reserved - [2] rffull the rxfifo full indicates the rxfifo is full due to four 64-byte packets are kept in rxfifo and the following incoming packet will be dropped. 1?b0: the rxfifo is not full. 1?b1: the rxfifo is full and the following incoming packet will be dropped. [1] rxha the receive halted high indicates the next normal packet reception process will be halted because the bit rxon of mcmdr is disabled be s/w. 1?b0: next normal packet reception process will go on. 1?b1: next normal packet reception process will be halted. [0] cfr the control frame received high indica tes emc receives a flow control frame. the cfr only available while emc is operating on full duplex mode. 1?b0: the emc doesn?t receive the flow control frame. 1?b1: the emc receives a flow control frame. free datasheet http:///
W90N745cd/W90N745cdg - 144 - missed packet count register (mpcnt) the mpcnt keeps the number of packets that were dropped due to various types of receive errors. the mpcnt is a read clear register. in addition, s/ w also can write an initial value to mpcnt and the missed packet counter will start counting from that initial value. if the missed packet counter is overflow, the mmp of mista will be set. register address r/w description reset value mpcnt 0xfff0_30b8 r/w miss ed packet count register 0x0000_7fff 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 mpc 7 6 5 4 3 2 1 0 mpc bits descriptions [31:16] reserved - [15:0] mpc the miss packet count indicates the number of packets that were dropped due to various types of receive errors. the following type of receiving error makes missed packet counter increase: ? incoming packet is incurred rxfifo overflow. ? incoming packet is dropped due to rxon is disabled. ? incoming packet is incurred crc error. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 145 - revision a2 mac receive pause count register (mrpc) the emc of W90N745 supports the pause control fr ame reception and recognition. if emc received a pause control frame, the operand field of the pau se control frame will be extracted and stored in the mrpc register. the mrpc r egister will keep the same while tx of emc is pausing due to the pause control frame is received. the mrpc is read only and write to this register has no effect. register address r/w description reset value mrpc 0xfff0_30bc r mac rece ive pause count register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 mrpc 7 6 5 4 3 2 1 0 mrpc bits descriptions [31:16] reserved - [15:0] mrpc the mac receive pause count keeps the operand field of the pause control frame. it indicates how many slot time (512 bit time) the tx of emc will be paused. mac receive pause current count register (mrpcc) the emc of W90N745 supports the pause control fr ame reception and recognition. if emc received a pause control frame, the operand field of the pau se control frame will be extracted and stored into a down count timer. the mrpcc shows the current va lue of that down count timer for s/w to know how long the tx of emc will be paused. the mrpcc is read only and write to this register has no effect. register address r/w description reset value mrpcc 0xfff0_30c0 r mac receive pause current count register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 146 - 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 mrpcc 7 6 5 4 3 2 1 0 mrpcc bits descriptions [31:16] reserved - [15:0] mrpcc the mac receive pause current count shows the current value of that down count timer. if a new pause control frame is received before the timer count down to zero, the new operand of the pause control frame will be stored into the down count timer and the timer starts count down from the new value. mac remote pause count register (mrepc) the emc of W90N745 supports the pause control frame transmission. after the pause control frame is transmitted out completely, a timer starts to count down from the value of operand of the transmitted pause control frame. t he mrepc shows the current value of this down count timer. the mrepc is read only and write to this register has no effect. register address r/w description reset value mrepc 0xfff0_30c4 r mac remote pause count register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 mrepc 7 6 5 4 3 2 1 0 mrepc free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 147 - revision a2 bits descriptions [31:16] reserved [15:0] mrepc the mac remote pause count shows the current value of the down count timer that starts to count down from the value of operand of the transmitted pause control frame. dma receive frame status register (dmarfs) the dmarfs is used to keep the length/type field of each incoming ethernet packet. this register is writing clear and writes 1 to corresponding bit clears the bit. register address r/w description reset value dmarfs 0xfff0_30c8 r/w dma rece ive frame status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rxflt 7 6 5 4 3 2 1 0 rxflt bits descriptions [31:16] reserved [15:0] rxflt the receive frame length/type k eeps the length/type field of each incoming ethernet packet. if the bit enden of mien is enabled and the length/type field of incomi ng packet has received, the bit deni of mista will be set and trigger interrupt. and, the content of length/type field will be stored in rxflt. free datasheet http:///
W90N745cd/W90N745cdg - 148 - current transmit descriptor start address register (ctxdsa) the ctxdsa keeps the start address of tx descripto r that is used by txdma currently. the ctxdsa is read only and write to this register has no effect. register address r/w description reset value ctxdsa 0xfff0_30cc r current transmit descriptor start address register 0x0000_0000 31 30 29 28 27 26 25 24 ctxdsa 23 22 21 20 19 18 17 16 ctxdsa 15 14 13 12 11 10 9 8 ctxdsa 7 6 5 4 3 2 1 0 ctxdsa bits descriptions [31:0] ctxdsa current transmit descriptor start address current transmit buffer start address register (ctxbsa) the ctxdsa keeps the start address of tx frame buffer that is used by txdma currently. the ctxbsa is read only and write to th is register has no effect. register address r/w description reset value ctxbsa 0xfff0_30d0 r current transmit buffer start address register 0x0000_0000 31 30 29 28 27 26 25 24 ctxbsa 23 22 21 20 19 18 17 16 ctxbsa 15 14 13 12 11 10 9 8 ctxbsa 7 6 5 4 3 2 1 0 ctxbsa free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 149 - revision a2 bits descriptions [31:0] ctxbsa current transmit buffer start address current receive descriptor star t address register (crxdsa) the crxdsa keeps the start address of rx descr iptor that is used by rxdma currently. the crxdsa is read only and write to this register has no effect. register address r/w description reset value crxdsa 0xfff0_30d4 r current receive descriptor start address register 0x0000_0000 31 30 29 28 27 26 25 24 crxdsa 23 22 21 20 19 18 17 16 crxdsa 15 14 13 12 11 10 9 8 crxdsa 7 6 5 4 3 2 1 0 crxdsa bits descriptions [31:0] crxdsa current receive descriptor start address current receive buffer start address register (crxbsa) the crxbsa keeps the start address of rx frame buffer that is used by rxdma currently. the crxbsa is read only and write to th is register has no effect. register address r/w description reset value crxbsa 0xfff0_30d8 r current receive buffer start address register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 150 - 31 30 29 28 27 26 25 24 crxbsa 23 22 21 20 19 18 17 16 crxbsa 15 14 13 12 11 10 9 8 crxbsa 7 6 5 4 3 2 1 0 crxbsa bits descriptions [31:0] crxbsa current receive buffer start address receive finite state machine register (rxfsm) the rxfsm shows the current value of the fsm (finite state machine) of rxdma and rxfifo controller. the rxfsm is read only and write to it has no effect. the rxfsm is used only for debug. register address r/w description reset value rxfsm 0xfff0_3200 r receive fini te state machine register 0x0081_1101 31 30 29 28 27 26 25 24 rx_fsm 23 22 21 20 19 18 17 16 rx_fsm reserved rxbuf_fsm 15 14 13 12 11 10 9 8 rxfetch_fsm rxclose_fsm 7 6 5 4 3 2 1 0 rff_fsm free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 151 - revision a2 bits descriptions [31:23] rx_fsm rxdma fsm [22] reserved - [21:16] rxbuf_fsm receive buffer fsm [15:12] rxfetch_fsm receive descriptor fetch fsm [11:8] rxclose_fsm rece ive descriptor close fsm [7:0] rff_fsm rxfifo controller fsm transmit finite state machine register (txfsm) the txfsm shows the current value of the fsm (finite state machine) of txdma and txfifo controller. the txfsm is read only and write to it has no effect. the txfsm is used only for debug. register address r/w description reset value txfsm 0xfff0_3204 r transmit finite state machine register 0x0101_1101 31 30 29 28 27 26 25 24 tx_fsm 23 22 21 20 19 18 17 16 reserved txbuf_fsm 15 14 13 12 11 10 9 8 txfetch_fsm txclose_fsm 7 6 5 4 3 2 1 0 reserved tff_fsm free datasheet http:///
W90N745cd/W90N745cdg - 152 - bits descriptions [31:24] tx_fsm txdma fsm [23:22] reserved - [21:16] txbuf_fsm transmit buffer fsm [15:12] txfetch_fsm transmit descriptor fetch fsm [11:8] txclose_fsm transmit descriptor close fsm [7:5] reserved - [4:0] tff_fsm txfifo controller fsm finite state machine register 0 (fsm0) the fsm0 shows the current value of the fsm (finit e state machine) of the function module in emc. the fsm0 is read only and write to it has no effect. the fsm0 is used only for debug. register address r/w description reset value fsm0 0xfff0_3208 r finite state machine register 0 0x0001_0101 31 30 29 28 27 26 25 24 reserved txmac_fsm 23 22 21 20 19 18 17 16 txmac_fsm 15 14 13 12 11 10 9 8 reserved txdefer_fsm 7 6 5 4 3 2 1 0 sta_fsm bits descriptions [31:26] reserved - [25:16] txmac_fsm txmac fsm [15:14] reserved - [13:8] txdefer_fsm transmit defer process fsm [7:0] sta_fsm mii management i/f fsm free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 153 - revision a2 finite state machine register 1 (fsm1) the fsm1 shows the current value of the fsm (finit e state machine) of the function module in emc. the fsm1 is read only and write to it has no effect. the fsm1 is used only for debug. register address r/w description reset value fsm1 0xfff0_320c r finite state machine register 1 0x1100_0100 31 30 29 28 27 26 25 24 reserved arb_fsm txpause_fsm 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved ahb_fsm 7 6 5 4 3 2 1 0 reserved bits descriptions [31] reserved - [30:28] arb_fsm internal arbiter fsm [27:24] txpause_fsm transmit pause control frame fsm [23:14] reserved - [13:8] ahb_fsm [13:8]: ahb master fsm [7:0] reserved - debug configuration register (dcr) the dcr is for debug only to multiplex different signal group out. in fpga emulation, the signals are outputted to probe pins in emulation board. in r eal chip, the signals are outputted through the gpio pins. register address r/w description reset value dcr 0xfff0_3210 r/w debug configuration register 0x0000_003f free datasheet http:///
W90N745cd/W90N745cdg - 154 - 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 enable reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 out config bits descriptions [31:24] reserved - [23:22] enable the function enable outputs two function enable signals to external stimulus circuit. at this stage, only the bit 22 is used for external random collision generator. the random collision generator used only in fpga emulation. [21:8] reserved - [7:6] out the flag out provides two output flags to trigger logic analyzer for debug. these two bits can be written at any time. [5:0] config the configuration controls which group of internal signals can be multiplexed out for debug. each group includes 16 signals. config signals config signals 6?h00 out [6], transdone, grantlost, trans_ctr [4:0], last, transctrexpire, dmode_ahb_cs [5:0] 6?h01 out [6], dmode_txbuf_cs [6:0] dmode_txfsm_cs [7:0] 6?h02 out [6], dmode_rxbuf_cs [5:0], dmode_rxfsm_cs [8:0] 6?h03 out [6], txfifo_ht, txfifo_lt, dmode_tff_cs [4:0], dmode_rff_cs [7:0] 6?h04 txbuf_drdy, tff_wptr [5:0], tx_start, txstart, read, tff_rptr [5:0] 6?h05 write, rff_wptr [5:0], rxfifo_ht, rxfifo_lt, rxbuf_ack, rff_rptr [5:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 155 - revision a2 continued. config signals config signals 6?h06 r0_ptle, rxstart, sfd, wassfd, rxframe, wrbyte, rx_ovflow, 1?b0, r0_rbc [7:0] 6?h07 r0_crce, rx_dv_in, synstart, r0_db, rx_ovflow, writectr [2:0], rxbyte [7:0] 6?h08 reserved 6?h09 reserved 6?h0a out [7:6], regmista_rx_w, rxerr_sync, r0_crce, r0_ptle, r0_rp, regmista_tx_w, t0_exdef, t0_txabt, t0_ccnt [3:0], 2?b00 6?h0b out [7:6], mcmdr_sdpz_clr, regmcmdr_sdpz_clr, dmode_pause_cs [3:0], macctlfra, pausefra, pausetx, macctlfra_sync, pausefra_sync, pause, pause_en, fdup 6?h0c out [7:6], framewptr [1:0], framerptr [1:0], rff_one, framewptr_inc, framerptr_inc, rounding, nexpktstartptr [5:0] 6?h0d out [7:6], arb_req_set, arb_req_clr, dmode_arb_cs [2:0], transdone, grantlost, transctrexpire, trans_ctr [4:0], burst 6?h0e r0_crce, rx_ovflow, r0_mre, crcerr, damatch, rxframe, sfd, rxmiierr, synstart, hi_lo_syn, new_datavalid, l_rxframe, rxstart, datavalid, hi_lo, rx_dv_in 6?h0f out [6], write, rff_wptr [5:0], rxreuse, rxbuf_ack, rff_rptr [5:0] 6?h10 write, rff_cs [7:1], rff_wptr [5:0], rxerr_sync, rxreuse 6?h11 out [6], tx_clk, tx_en, txd [3:0], rx_clk, rx_dv, rx_er, rxd [3:0], crs, col 6?h12 out [6], txstart, tx_start, dmode_tff_cs [4:0], txstart_set, txstart_clr, txstart_re_set, framewaiting, deferring, col, txcol, txcol_sync 6?h13 out [6], dmode_txbuf_cs[6:0], dmode_tff_cs[4:0], txfifo_uf, txfifo_ht, txok_sync 6?h14 out [6], read, read_sync, read_mask, readmask_sync, tff_rptr [5:0], dmode_tff_cs [4:0] 6?h15 free datasheet http:///
W90N745cd/W90N745cdg - 156 - debug mode mac information register (dmmir) the dmmir keeps the informat ion of mac module for debug. register address r/w description reset value dmmir 0xfff0_3214 r debug mode mac information register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rbc 7 6 5 4 3 2 1 0 rbc bits descriptions [31:16] reserved - [15:0] rbc receive byte count bist mode register (bistr) the bistr controls the bist (built in self test) for embedded sram, 256b for rxfifo and 256b for txfifo. register address r/w description reset value bistr 0xfff0_3300 r/w bist mode register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved bistfail finish bmen free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 157 - revision a2 bits descriptions [31:5] reserved - [3:2] bistfail the bist fail indicates if the bist test fails or succeeds. if the bistfail is low at the end, the embedded sram pass the bist test, otherwise, it is faulty. the bistfail will be high once the bist detects the error and remains high during the bist operation. if bistfail[2] high indicates the embedded sram for txfifo bist test failed. if bistfail[3] high indicates the embedded sram for rxfifo bist test failed. the bistfail is a write clear field. write 1 to this field clears the content and write 0 has no effect. [1] finish the bist operation finish indicates the end of the bist operation. when bist controller fini shes all operations, this bit will be high. the finish is a write clear field. write 1 to this field clears the content and write 0 has no effect. [0] bmen the bist mode enable is used to enable the bist operation. if high enables the bist controller to do embedded sram test. this bit is also used to do the reset for bist circuit. it is necessary to reset the bist circuit one clock cycle at least in order to initialize the bist properly. the bmen can be disabled by write 0. free datasheet http:///
W90N745cd/W90N745cdg - 158 - 6.6 gdma controller the W90N745 has a two-channel general dma contro ller, called the gdma. the two-channel gdma performs the following data transfers without the cpu intervention: y memory-to-memory (memory to/from memory) y memory ?to ? io y io- to -memory the on-chip gdma can be started by the software or external dma request nxdreq. software can also be used to restart the gdma operation after it has been stopped. the cpu can recognize the completion of a gdma operation by software polling or when it receives an internal gdma interrupt. the W90N745 gdma controller can increment source or destinat ion address, decrement them as well, and conduct 8- bit (byte), 16-bit (half-word), or 32-bit (word) data transfers. the gdma includes the following features y amba ahb compliant y supports 4-data burst mode to boost performance y provides support for external gdma device y demand mode speeds up external gdma operations 6.6.1 gdma functional description the gdma directly transfers data between source and destination. the gdma starts to transfer data after it receives service requests from nxdre q signal or software. when the entire data have been transferred completely, the gdma becomes idle. ne vertheless, if another tr ansfer is needed, then the gdma must be programmed again. there are three transfer modes: single mode single mode requires a gdma request for each data transfer. a gdma request (nxdreq or software) causes one byte, one half-word, or one wo rd to transfer if the 4-data burst mode is disabled, or four times of transfer wi dth is the 4-data burst mode is enabled. block mode the assertion of a single gdma request causes all of the data to be transferred in a single operation. the gdma transfer is completed when t he current transfer count register reaches zero. demand mode the gdma continues transferring data until the gdma request input nxdreq becomes inactive. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 159 - revision a2 6.6.2 gdma register map r : read only, w : write only, r/w : both read and write, c : only value 0 can be written register address r/w description reset value channel 0 gdma_ctl0 0xfff0_4000 r/w channel 0 control register 0x0000_0000 gdma_srcb0 0xfff0_4004 r/w channel 0 source base address register 0x0000_0000 gdma_dstb0 0xfff0_4008 r/w channel 0 destination base address register 0x0000_0000 gdma_tcnt0 0xfff0_400c r/w channel 0 transfer count register 0x0000_0000 gdma_csrc0 0xfff0_4010 r channel 0 current source address register 0x0000_0000 gdma_cdst0 0xfff0_4014 r channel 0 current destination address register 0x0000_0000 gdma_ctcnt0 0xfff0_4018 r channel 0 current transfer count register 0x0000_0000 channel 1 gdma_ctl1 0xfff0_4020 r/w channel 1 control register 0x0000_0000 gdma_srcb1 0xfff0_4024 r/w channel 1 source base address register 0x0000_0000 gdma_dstb1 0xfff0_4028 r/w channel 1 destination base address register 0x0000_0000 gdma_tcnt1 0xfff0_402c r/w channel 1 transfer count register 0x0000_0000 gdma_csrc1 0xfff0_4030 r channel 1 current source address register 0x0000_0000 gdma_cdst1 0xfff0_4034 r channel 1 current destination address register 0x0000_0000 gdma_ctcnt1 0xfff0_4038 r channel 1 current transfer count register 0x0000_0000 channel 0/1 control register (gdma_ctl0, gdma_ctl1) register address r/w description reset value gdma_ctl0 0xfff0_4000 r/w channel 0 control register 0x0000_0000 gdma_ctl1 0xfff0_4020 r/w channel 1 control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved tc_width req_sel req_atv ack_atv 23 22 21 20 19 18 17 16 rw_tc sabnderr dabnderr gdmaer r autoien tc block softreq 15 14 13 12 11 10 9 8 dm reserved tws sbms r eserve d bme sien 7 6 5 4 3 2 1 0 safix dafix sadir dadir gdmams reserved gdmaen free datasheet http:///
W90N745cd/W90N745cdg - 160 - bits descriptions [31] reserved - [30:28] tc_width nrtc/nwtc active width selection, from 1 to 7 hclk cycles. [27:26] req_sel external request pin selection, if gdmams [3:2]=00, req_sel will be don?t care. if req_sel [27:26]=00, external request don?t use. if req_sel [27:26]=01, use nxdreq. if req_sel [27:26]=10, external request don?t use. if req_sel [27:26]=11, external request don?t use. [25] req_atv nxdreq high/low active selection 1?b0 = nxdreq is low active. 1?b1 = nxdreq is high active. [24] ack_atv nxdack high/low active selection 1?b0 = nxdack is low active. 1?b1 = nxdack is high active. [23] rw_tc read/write terminal count output selection. 1?b0 = output to nrtc. 1?b1 = output to nwtc. [22] sabnderr source address boundary alignment error flag if tws [13:12]=10, gdma_srcb [1:0] should be 00 if tws [13:12]=01, gdma_srcb [0] should be 0 the address boundary alignment should be depended on tws [13:12]. 1?b0 = the gdma_srcb is on the boundary alignment. 1?b1 = the gdma_srcb not on the boundary alignment the sabnderr register bits just can be read only. [21] dabnderr destination address boundary alignment error flag if tws [13:12]=10, gdma_dstb [1:0] should be 00 if tws [13:12]=01, gdma_dstb [0] should be 0 the address boundary alignment should be depended on tws [13:12]. 1?b0 = the gdma_dstb is on the boundary alignment. 1?b1 = the gdma_dstb not on the boundary alignment the dabnderr register bits just can be read only. [20] gdmaterr gdma transfer error 1?b0 = no error occurs 1?b1 = hardware sets this bit on a gdma transfer failure transfer error will generate gdma interrupt free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 161 - revision a2 continued bits descriptions [19] autoien auto initialization enable 1?b0 = disables auto initialization 1?b1 = enables auto initializ ation, the gdma_csrc0/1, gdma_cdst0/1,and gdma_ctcnt0/ 1 registers are updated by the gdma_src0/1,gdma_dst0/1, and gdma_tcnt0/1 registers automatically when transfer is complete. [18] tc terminal count 1?b0 = channel does not expire 1?b1 = channel expires; this bit is set only by gdma hardware, and clear by software to write logic 0. tc [18] is the gdma interrupt fl ag. tc [18] or gdmaterr[20] will generate interrupt [17] block bus lock 1?b0 = unlocks the bus during the period of transfer 1?b1 = locks the bus during the period of transfer [16] softreq software triggered gdma request software can request the gdma transfer service by setting this bit to 1. this bit is automatically cleared by hardware when the transfer is completed. this bit is available only while gdmams [3:2] register bits are set on software mode (memory to memory). [15] dm demand mode 1?b0 = normal external gdma mode 1?b1 = when this bit is set to 1, the external gdma operation is speeded up. when external gdma device is operating in the demand mode, the gdma transfers data as long as the external gdma request signal nxdreq is active. the amount of data transferred depends on how long the nxdreq is active. when the nx dreq is active and gdma gets the bus in demand mode, dma holds the system bus until the nxdreq signal becomes non-active. therefore, the period of the active nxdreq signal should be carefully tuned such that the entire operation does not exceed an acceptable interval (for example, in a dram refresh operation). [14] reserved - free datasheet http:///
W90N745cd/W90N745cdg - 162 - continued bits descriptions [13:12] tws transfer width select 00 = one byte (8 bits) is trans ferred for every gdma operation 01 = one half-word (16 bits) is tr ansferred for every gdma operation 10 = one word (32 bits) is transferred for every gdma operation 11 = reserved the gdma_scrb and gdma_dstb should be alignment under the tws selection [11] sbms single/block mode select 1?b0 = selects single mode. it requires an external gdma request for every incurring gdma operation. 1?b1 = selects block mode. it require s a single external gdma request during the atomic gdma operation. an atomic gdma operation is defined as the sequence of gdma operations until the transfer count register reaches zero. [10] reserved - [9] bme burst mode enable 1?b0 = disables the 4-data burst mode 1?b1 = enables the 4-data burst mode ff there are 16 words to be transferred, and bme [9]=1, the gdma_tcnt should be 0x04; however, if bme [9]=0, the gdma_tcnt should be 0x10. [8] sien stop interrupt enable 1?b0 = do not generate an interrupt when the gdma operation is stopped 1?b1 = interrupt is generated when the gdma operation is stopped [7] safix source address fixed 1?b0 = source address is changed during the gdma operation 1?b1 = do not change the desti nation address during the gdma operation. this feature can be used when data were transferred from a single source to multiple destinations. [6] dafix destination address fixed 1?b0 = destination address is changed during the gdma operation 1?b1 = do not change the destinat ion address during the gdma operation. this feature can be us ed when data were transferred from multiple sources to a single destination. [5] sadir source address direction 1?b0 = source address is incremented successively 1?b1 = source address is decremented successively free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 163 - revision a2 continued bits descriptions [4] dadir destination address direction 1?b0 = destination address is incremented successively 1?b1 = destination address is decremented successively [3:2] gdmams gdma mode select 00 = software mode (memory-to-memory) 01 = external nxdreq mode for external device 10 = reserved 11 = reserved [1] reserved - [0] gdmaen gdma enable 1?b0 = disables the gdma operation 1?b1 = enables the gdma operation; th is bit will be clear automatically when the transfer is complete on autoie n [19] register bit is on disable mode. channel 0/1 source base address register (gdma_srcb0, gdma_srcb1) the gdma channel starts reading its data from the source address as defined in this source base address register. register address r/w description reset value gdma_srcb0 0xfff0_4004 r/w channel 0 source base address register 0x0000_0000 gdma_srcb1 0xfff0_4024 r/w channel 1 source base address register 0x0000_0000 31 30 29 28 27 26 25 24 src_base_addr [31:24] 23 22 21 20 19 18 17 16 src_base_addr [23:16] 15 14 13 12 11 10 9 8 src_base_addr [15:8] 7 6 5 4 3 2 1 0 src_base_addr [7:0] bits descriptions [31:0] src_base_addr 32-bit source base address free datasheet http:///
W90N745cd/W90N745cdg - 164 - channel 0/1 destination base address re gister (gdma_dstb0, dma_dstb1) channel 0/1 destination base address register (gdma_dstb0, gdma_dstb1) the gdma channel starts writing its data to the des tination address as defined in this destination base address register. during a block transfer, the gd ma determines successive destination addresses by adding to or subtracting from the destination base address. register address r/w description reset value gdma_dstb0 0xfff0_4008 r/w channel 0 destination base address register 0x0000_0000 gdma_dstb1 0xfff0_4028 r/w channel 1 destination base address register 0x0000_0000 31 30 29 28 27 26 25 24 dst_base_addr [31:24] 23 22 21 20 19 18 17 16 dst_base_addr [23:16] 15 14 13 12 11 10 9 8 dst_base_addr [15:8] 7 6 5 4 3 2 1 0 dst_base_addr [7:0] bits descriptions [31:0] dst_base_addr 32-bit de stination base address channel 0/1 transfer count regi ster (gdma_tcnt0, gdma_tcnt1) register address r/w description reset value gdma_tcnt0 0xfff0_400c r/w channel 0 transfer count register 0x0000_0000 gdma_tcnt1 0xfff0_402c r/w channel 1 transfer count register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 tfr_cnt [23:16] 15 14 13 12 11 10 9 8 tfr_cnt [15:8] 7 6 5 4 3 2 1 0 tfr_cnt [7:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 165 - revision a2 bits descriptions [31:24] reserved - [23:0] tfr_cnt the tfr_cnt represents the required number of gdma transfers. the maximum tr ansfer count is 16m ?1. channel 0/1 current source register (gdma_csrc0, gdma_csrc1) register address r/w description reset value gdma_csrc0 0xfff0_4010 r channel 0 current source address register 0x0000_0000 gdma_csrc1 0xfff0_4030 r channel 1 current source address register 0x0000_0000 31 30 29 28 27 26 25 24 current_src_addr [31:24] 23 22 21 20 19 18 17 16 current_src_addr [23:16] 15 14 13 12 11 10 9 8 current_src_addr [15:8] 7 6 5 4 3 2 1 0 current_src_addr [7:0] bits descriptions [31:0] current_src_addr the 32-bit current source address indicates the source address where the gdma transfer is just occurring. during a block transfer, the gdma determines the successive source addresses by adding to or subtracting from the source base address. depending on the settings you make to the control register, the current source address will remain the same or will be incremented or decremented. free datasheet http:///
W90N745cd/W90N745cdg - 166 - channel 0/1 current destination re gister (gdma_cdst0, gdma_cdst1) register address r/w description reset value gdma_cdst0 0xfff0_4014 r channel 0 current destination address register 0x0000_0000 gdma_cdst1 0xfff0_4034 r channel 1 current destination address register 0x0000_0000 31 30 29 28 27 26 25 24 current_dst_addr [31:24] 23 22 21 20 19 18 17 16 current_dst_addr [23:16] 15 14 13 12 11 10 9 8 current_dst_addr [15:8] 7 6 5 4 3 2 1 0 current_dst_addr [7:0] bits descriptions [31:0] current_dst_addr the 32-bit current destination address indicates the destination address where the gdma transfer is just occurring. during a block trans fer, the gdma determines the successive destination addresses by adding to or subtracting from the desti nation base address. depending on the settings you make to the control register, the current destination address will remain the same or will be incremented or decremented. channel 0/1 current transfer count register (gdma_ctcnt0, gdma_ctcnt1) the current transfer count register indica tes the number of transfer being performed. register address r/w description reset value gdma_ctcnt0 0xfff0_4018 r channel 0 current transfer count register 0x0000_0000 gdma_ctcnt1 0xfff0_4038 r channel 1 current transfer count register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 167 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 curent_tfr_cnt [23:16] 15 14 13 12 11 10 9 8 current_tfr_cnt [15:8] 7 6 5 4 3 2 1 0 current_tfr_cnt [7:0] bits descriptions [31:24] reserved - [23:0] current_tfr_cnt current transfer count register the current transfer count regi ster indicates the number of transfer being performed free datasheet http:///
W90N745cd/W90N745cdg - 168 - 6.7 usb host controller the universal serial bus (usb) is a low-cost, low-to-mid-speed peripheral interface standard intended for modem, scanners, pdas, keyboards, mice , and other devices that do not require a high- bandwidth parallel interface. the usb is a 4-wire serial cable bus that supports serial data exchange between a host controller and a network of peripher al devices. the attached peripherals share usb bandwidth through a host-scheduled, token-based protoc ol. peripherals may be attached, configured, used, and detached, while the host and other peri pherals continue operation (i.e. hot plug and unplug is supported). a major design goal of the usb standard was to allow flexible, plug-and-play networks of usb devices. in any usb network, there will be only one host, but there can be many devices and hubs. the usb host controller has the following features: ? open host controller interface (ohci) revision 1.1 compatible. ? usb revision 1.1 compatible ? supports both low-speed (1.5 mbps ) and full-speed (12mbps) usb devices. ? handles all the usb protocol. ? built-in dma for real-time data transfer ? multiple low power modes for efficient power management 6.7.1 usb host functional description 6.7.1.1. ahb interface the openhci host controller is connected to the system by the ahb bus. the design requires both master and slave bus operations. as a master, the host controller is responsible for running cycles on the ahb bus to access eds and tds as well as transferring data between memory and the local data buffer. as a slave, the ho st controller monitors the cycles on the ahb bus and determines when to respond to these cycles. configuration and non-r eal-time control access to the host controller operational registers are through the ahb bus slave interface. 6.7.1.2. host controller list processing the list processor manages the data structures from the host cont roller driver and coordinates all activity within the host controller. frame management frame management is responsible for managing t he frame specific tasks required by the usb specification and the openhci spec ification. these tasks are: 1) management of the openhci frame specific operational registers 2) operation of the largest data packet counter. 3) performing frame qualifications on usb transaction reques ts to the sie. 4) generate sof token requests to the sie. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 169 - revision a2 interrupt processing interrupts are the communication method for hc-init iated communication with the host controller driver. there are several events that may trigger an in terrupt from the host controller. each specific event sets a specific bit in the hcinterruptstatus register. host controller bus master the host controller bus master is the central blo ck in the data path. the ho st controller bus master coordinates all access to the ahb interface. ther e are two sources of bus mastering within host controller: the list processor and the data buffer engine. data buffer the data buffer serves as the data interface betw een the bus master and the sie. it is a combination of a 64-byte latched based bi-directional asyn chronous fifo and a single dword ahb holding register. 6.7.1.3. usb interface the usb interface includes the integrated root hub wi th two external ports, port 1 and port 2 as well as the serial interface engine (sie) and usb clo ck generator. the interface combines responsibility for executing bus transactions requested by the hc as well as the hub and port management specified by usb. 6.7.2 usb host controller registers map register address r/w description reset value openhci registers hcrevision 0xfff0_5000 r host controller revision register 0x0000_0010 hccontrol 0xfff0_5004 r/w host controller control register 0x0000_0000 hccommandstatus 0xfff0_5008 r/w host controller command status register 0x0000_0000 hcinterruptstatus 0xfff0_500c r/w host controller interrupt status register 0x0000_0000 hcinterruptenbale 0xfff0_5010 r/w host controller interrupt enable register 0x0000_0000 hcinterruptdisbale 0xfff0_5014 r/w host controller interrupt disable register 0x0000_0000 hchcca 0xfff0_5018 r/w host controller communication area register 0x0000_0000 hcperiodcurrented 0xfff0_501c r/w host controller period current ed register 0x0000_0000 hccontrolheaded 0xfff0_5020 r/w host controller control head ed register 0x0000_0000 hccontrolcurrented 0xfff0_5024 r/w host controller control current ed register 0x0000_0000 hcbulkheaded 0xfff0_5028 r/w host controller bulk head ed register 0x0000_0000 hcbulkcurrented 0xfff0_502c r/w host controller bulk current ed register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 170 - continued. register address r/w description reset value openhci registers hcdoneheaded 0xfff0_5030 r/w host cont roller done head register 0x0000_0000 hcfminterval 0xfff0_5034 r/w host controlle r frame interval register 0x0000_2edf hcframeremaining 0xfff0_5038 r host controller frame remaining register 0x0000_0000 hcfmnumber 0xfff0_503c r host controller frame number register 0x0000_0000 hcperiodicstart 0xfff0_5040 r/w host cont roller periodic start register 0x0000_0000 hclsthreshold 0xfff0_5044 r/w host controller low speed threshold register 0x0000_0628 hcrhdescriptora 0xfff0_5048 r/w host controller root hub descriptor a register 0x0100_0002 hcrhdescriptorb 0xfff0_504c r/w host controller root hub descriptor b register 0x0000_0000 hcrhstatus 0xfff0_5050 r/w host controller root hub status register 0x0000_0000 hcrhportstatus [1] 0xfff0_5054 r/w host controller root hub port status [1] 0x0000_0000 hcrhportstatus [2] 0xfff0_5058 r/w host controller root hub port status [2] 0x0000_0000 usb configuration registers testmodeenable 0xfff0_5200 r/w usb test mode enable register 0x0xxx_xxxx operationalmodeenabl e 0xfff0_5204 r/w usb operational mode enable register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 171 - revision a2 host controller revision register register offset address r/w description reset value hcrevision 0xfff0_5000 r host controller revision register 0x0000_0010 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 revision bits description [31:8] reserved reserved. read/write 0's [7:0] revision indicates the open hci specific ation revision number implemented by the hardware. host contro ller supports 1.0 specification. (x.y = xyh) host controller control register register address r/w description reset value hccontrol 0xfff0_5004 r/w host controller control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved rwce rwc ir 7 6 5 4 3 2 1 0 hcfs ble cle ise ple cbr free datasheet http:///
W90N745cd/W90N745cdg - 172 - bits description [31:11] reserved reserved. read/write 0's [10] rwce remotewakeupconnectedenable if a remote wakeup signal is supported, this bit enables that operation. since there is no remote wakeup signal supported, this bit is ignored. [9] rwc remotewakeupconnected this bit indicated whether the hc supports a remote wakeup signal. this implementation does not support any such signal. the bit is hard-coded to ?0.? [8] inr interruptrouting this bit is used for interrupt routing: 0: interrupts routed to normal interrupt mechanism (int). 1: interrupts routed to smi. [7:6] hcfs hostcontrollerfunctionalstate this field sets the host controller st ate. the controller may force a state change from usb s uspend to usb r esume after detecting resume signaling from a downstream port. states are: 00: usb r eset 01: u sb r esume 10: u sb o perational 11: u sb s uspend [5] ble bulklistenable when set this bit enables pr ocessing of the bulk list. [4] cle control listenable when set this bit enables processing of the control list. [3] ise isochronous enable when clear, this bit disables the isoc hronous list when the periodic list is enabled (so interrupt eds may be serviced). while processing the periodic list, the host controller will check this bit when it finds an isochronous ed. [2] ple periodic listenable when set, this bit enables processing of the periodic (interrupt and isochronous) list. the host controller checks this bit prior to attempting any periodic transfers in a frame. [1:0] cbr controlbulkserviceratio specifies the number of control endpoints serviced for every bulk endpoint. encoding is n-1 where n is the number of control endpoints (i.e. ?00? = 1 control endpoint; ?11? = 3 control endpoints) free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 173 - revision a2 host controller command status register register address r/w description reset value hccommandstatus 0xfff0_5008 r/w host controller command status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ocr blf clf hcr bits description [31:18] reserved reserved [17:16] soc scheduleoverruncount this field is increment every time the schedulingoverrun bit in hcinterruptstatus is set. the count wraps from ?11? to ?00.? [15:4] reserved reserved. read/write 0's [3] ocr ownershipchangerequest when set by software, this bit sets the ownershipchange field in hcinterruptstatus . the bit is cleared by software. [2] blf bulklistfilled set to indicate there is an active ed on the bulk list. the bit may be set by either software or the host controller and cleared by the host controller each time it begins proc essing the head of the bulk list. [1] clf controllistfilled set to indicate there is an active ed on the control list. it may be set by either software or the host controller and cleared by the host controller each time it begins proc essing the head of the control list. [0] hcr hostcontrollerreset this bit is set to initiate the softw are reset. this bit is cleared by the host controller, upon complet ed of the reset operation. free datasheet http:///
W90N745cd/W90N745cdg - 174 - host controller interrupt status register all bits are set by hardware and cleared by software. register address r/w description reset value hcinterruptstatus 0xfff0_500c r/w host controller interr upt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved och reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved rhsc fno ure rdt sof wdh sco bits description [31] reserved reserved [30] och ownershipchange this bit is set when the ownershipchangerequest bit of hccommandstatus is set. [29:7] reserved [6] rhsc roothubstatuschange this bit is set when the content of hcrhstatus or the content of any hcrhportstatus register has changed. [5] fno framenumberoverflow set when bit 15 of framenumber changes value. [4] ure unrecoverableerror this event is not implemented and is hard-coded to ?0.? writes are ignored. [3] rdt resumedetected set when host controller detects resume signaling on a downstream port. [2] sof startofframe set when the frame management blo ck signals a ?start of frame? event. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 175 - revision a2 continued. bits description [1] wdh writebackdonehead set after the host controller has written hcdonehead to hccadonehead . [0] scho schedulingoverrun set when the list processor determines a schedule overrun has occurred. host controller interrupt enable register writing a ?1? to a bit in this register sets the corresponding bit, while writing a ?0? leaves the bit unchanged. register address r/w description reset value hcinterruptenable 0xfff0_5010 r/w host controller interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 mie oce reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved rhce fnoe uree rdte sofe wdhe schoe bits description [31] mie masterinterruptenable this bit is a global interrupt enable. a write of ?1? allows interrupts to be enabled via the specific enable bits listed above. [30] oce ownershipchangeenable 0: ignore 1: enable interrupt generation due to ownership change. [29:7] reserved reserved. read/write 0's [6] rhsce roothubstatuschangeenable 0: ignore 1: enable interrupt generation due to root hub status change. free datasheet http:///
W90N745cd/W90N745cdg - 176 - continued. bits description [5] fnoe framenumberoverflowenable 0: ignore 1: enable interrupt generation due to frame number overflow. [4] uree unrecoverableerrorenable this event is not implemented. a ll writes to this bit are ignored. [3] rdte resumedetectedenable 0: ignore 1: enable interrupt generation due to resume detected. [2] sofe startofframeenable 0: ignore 1: enable interrupt generation due to start of frame. [1] wdhe writebackdoneheadenable 0: ignore 1: enable interrupt generation due to write-back done head. [0] schoe schedulingoverrunenable 0: ignore 1: enable interrupt generation due to scheduling overrun. host controller interrupt disable register writing a ?1? to a bit in this register clears the corre sponding bit, while writing a ?0? to a bit leaves the bit unchanged. register address r/w description reset value hcinterruptenable 0xfff0_5014 r/w host controller interrupt disable register 0x0000_0000 31 30 29 28 27 26 25 24 mie oce reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved rhsce fnoe uree rdte sofe wdhe schoe free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 177 - revision a2 bits description [31] mie masterinterruptenable global interrupt disable. a write of ?1? disables all interrupts. [30] oce ownershipchangeenable 0: ignore 1: disable interrupt generation due to ownership change. [29:7] reserved reserved. read/write 0's [6] rhsce roothubstatuschangeenable 0: ignore 1: disable interrupt generation due to root hub status change. [5] fnoe framenumberoverflowenable 0: ignore 1: disable interrupt generation due to frame number overflow. [4] uree unrecoverableerrorenable this event is not implemented. all writes to this bit will be ignored. [3] rdte resumedetectedenable 0: ignore 1: disable interrupt generation due to resume detected. [2] sofe startofframeenable 0: ignore 1: disable interrupt generation due to start of frame. [1] wdhe writebackdoneheadenable 0: ignore 1: disable interrupt generation due to write-back done head. [0] schoe schedulingoverrunenable 0: ignore 1: disable interrupt generation due to scheduling overrun. free datasheet http:///
W90N745cd/W90N745cdg - 178 - host controller communication area register register address r/w description reset value hchcca 0xfff0_5018 r/w host controller communication area register 0x0000_0000 31 30 29 28 27 26 25 24 hcca 23 22 21 20 19 18 17 16 hcca 15 14 13 12 11 10 9 8 hcca 7 6 5 4 3 2 1 0 reserved bits description [31:8] hcca hcca pointer to hcca base address. [7:0] reserved reserved host controller period current ed register register address r/w description reset value hcperiodcurreted 0xfff0_501c r/w host controller period current ed register 0x0000_0000 31 30 29 28 27 26 25 24 pced 23 22 21 20 19 18 17 16 pced 15 14 13 12 11 10 9 8 pced 7 6 5 4 3 2 1 0 pced bits description [31:4] pced periodcurrented . pointer to the curr ent periodic list ed. [3:0] reserved reserved. read/write 0's free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 179 - revision a2 host controller control head ed register register address r/w description reset value hccontrolheaded 0xfff0_5020 r/w host controller control head ed register 0x0000_0000 31 30 29 28 27 26 25 24 ched 23 22 21 20 19 18 17 16 ched 15 14 13 12 11 10 9 8 ched 7 6 5 4 3 2 1 0 ched reserved bits description [31:4] ched controlheaded pointer to the control list head ed. [3:0] reserved reserved host controller control current ed register register offset address r/w description reset value hccontrol currented 0xfff0_5024 r/w host controller control current ed register 0x0000_0000 31 30 29 28 27 26 25 24 cced 23 22 21 20 19 18 17 16 cced 15 14 13 12 11 10 9 8 cced 7 6 5 4 3 2 1 0 cced reserved bits description [31:4] cced controlcurrented pointer to the current control list ed. [3:0] reserved reserved. read/write 0's free datasheet http:///
W90N745cd/W90N745cdg - 180 - host controller bulk head ed register register offset address r/w description reset value hcbulkheaded 0xfff0_5028 r/w host controller bulk head ed register 0x0000_0000 31 30 29 28 27 26 25 24 bhed 23 22 21 20 19 18 17 16 bhed 15 14 13 12 11 10 9 8 bhed 7 6 5 4 3 2 1 0 bhed reserved bits description [31:4] bhed bulkheaded . pointer to the bulk list head ed. [3:0] reserved reserved. read/write 0's host controller bulk current ed register register offset address r/w description reset value hcbulkcurrented 0xfff0_502c r/w host controller bulk current ed register 0x0000_0000 31 30 29 28 27 26 25 24 bced 23 22 21 20 19 18 17 16 bced 15 14 13 12 11 10 9 8 bced 7 6 5 4 3 2 1 0 bced reserved bits description [31:4] bced bulkcurrented . pointer to the current bulk list ed. [3:0] reserved reserved. read/write 0's free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 181 - revision a2 host controller done head register register address r/w description reset value hcdonehead 0xfff0_5030 r/w host controller done head register 0x0000_0000 31 30 29 28 27 26 25 24 dohd 23 22 21 20 19 18 17 16 dohd 15 14 13 12 11 10 9 8 dohd 7 6 5 4 3 2 1 0 dohd reserved bits description [31:4] dohd donehead . pointer to the current done list head ed. [3:0] reserved reserved. read/write 0's host controller frame interval register register address r/w description reset value hcfminterval 0xfff0_5034 r/w host controller frame in terval register 0x0000_2edf 31 30 29 28 27 26 25 24 fintvt fsldp 23 22 21 20 19 18 17 16 fsldp 15 14 13 12 11 10 9 8 reserved fintv 7 6 5 4 3 2 1 0 fintv free datasheet http:///
W90N745cd/W90N745cdg - 182 - bits description 31 fintvt frameintervaltoggle this bit is toggled by hcd when it loads a new value into frame interval . [30:16] fsldp fslargestdatapacket this field specifies a value that is loaded into the largest data packet counter at the beginni ng of each frame. [15:14] reserved reserved . read/write 0's [13:0] fintv frame interval this field specifies the length of a fr ame as (bit times - 1). for 12,000 bit times in a frame, a val ue of 11,999 is stored here. host controller frame remaining register register address r/w description reset value hcfminterval 0xfff0_5038 r host controller frame remaining register 0x0000_0000 31 30 29 28 27 26 25 24 frmt reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved frm 7 6 5 4 3 2 1 0 frm bits description [31] frmt frameremainingtoggle loaded with frameintervaltoggle when frame remaining is loaded. [30:14] reserved reserved. read/write 0's [13:0] frm frame remaining when the host controller is in the u sb o perational state, this 14-bit field decrements each 12 mhz clock period. when the count reac hes 0, (end of frame) the counter reloads with frame interval . in addition, the counter loads when the host controller transitions into u sb o perational . free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 183 - revision a2 host controller frame number register register address r/w description reset value hcfmnumber 0xfff0_503c r host controller frame number register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 frmn 7 6 5 4 3 2 1 0 frmn bits description [31:16] reserved reserved. read/write 0's [15:0] frmn framenumber this 16-bit incrementing counter fiel d is incremented coincident with the loading of frameremaining . the count rolls over from ?000fh? to ?0h.? host controller periodic start register register address r/w description reset value hcperiodicstart 0xfff0_5040 r/w host controller periodic start register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 perst 7 6 5 4 3 2 1 0 perst free datasheet http:///
W90N745cd/W90N745cdg - 184 - bits description [31:14] reserved reserved . read/write 0's [13:0] perst periodicstart this field contains a value used by the list processor to determine where in a frame the periodic list processing must begin. host controller low speed threshold register register address r/w description reset value hclsthreshold 0xfff0_5044 r/w host controller low speed threshold register 0x0000_0628 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved lsthreshold 7 6 5 4 3 2 1 0 lstreshold bits description [31:12] reserved rsvd. read/write 0's [11:0] lstreshold lsthreshold this field contains a value used by the frame management block to determine whether or not a low speed transaction c an be started in t he current frame. host controller root hub descriptor a register this register is only reset by a power-on reset. it is written during system init ialization to configure the root hub. this bit should not be written during normal operation. register address r/w description reset value hcrhdescriptora 0xfff0_5048 r/w host controller root hub descriptor a register 0x0100.0002 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 185 - revision a2 31 30 29 28 27 26 25 24 potpgt 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved ocpm ocpm devt npsw pswm 7 6 5 4 3 2 1 0 ndsp bits description [31:24] potpgt powerontopowergoodtime this field value is represented as the num ber of 2 ms intervals, which ensuring that the power switching is effective with in 2 ms. only bits [25:24] is implemented as r/w. the remaining bits are read only as ?0?. it is not expected that these bits be written to anything other than 1h, but lim ited adjustment is provided. this field should be written to support system implem entation. this field should always be written to a non-zero value. [23:13] reserved reserved. read/write 0's [12] nocp noovercurrentprotection global over-current reporting implemented in hydra-2. this bit should be written to support the external system por t over-current implementation. 0 = over-current status is reported 1 = over-current status is not reported [11] ocpm overcurrentprotectionmode global over-current reporting implemented in hydra-2. this bit should be written 0 and is only valid when noovercu rrentprotection is cleared. 0 = global over-current 1 = individual over-current [10] devt devicetype table of none-4is not a compound device. [9] npsw nopowerswitching global power switching implemented in hydra-2. this bit should be written to support the external system port power switching implementation. 0 = ports are power switched. 1 = ports are always powered on. [8] pswm powerswitchingmode global power switching mode implemented in hydra-2. this bit is only valid when nopowerswitching is cleared. this bit should be written '0'. 0 = global switching 1 = individual switching [7:0] ndsp numberdownstreamports table of none-4 supports two downstream ports. free datasheet http:///
W90N745cd/W90N745cdg - 186 - host controller root hub descriptor b register this register is only reset by a power-on reset. it is written during system init ialization to configure the root hub. these bits should not be written during normal operation. register address r/w description reset value hcrhdescriptorb 0xfff0_504c r/w host controller root hub descriptor b register 0x0000_0000 31 30 29 28 27 26 25 24 ppcm 23 22 21 20 19 18 17 16 ppcm 15 14 13 12 11 10 9 8 devrm 7 6 5 4 3 2 1 0 devrm bits description [31:16] ppcm portpowercontrolmask global-power switching. this field is only valid if nopowerswitching is cleared and powerswitchingmode is set (individual port switching). when set, the port only responds to individual port power switching commands ( set / clearportpower ). when cleared, the port only responds to global power switching commands ( set / clearglobalpower ). 0 = device not removable 1 = global-power mask port bit relationship - unimplemented ports are reserved, read/write '0'. 0 : reserved 1 : port 1 2 : port 2 ... 15 : port 15 [15:0] devrm deviceremoveable table of none-4 ports default to removable devices. 0 = device not removable 1 = device removable port bit relationship 0 : reserved 1 : port 1 2 : port 2 ... 15 : port 15 unimplemented ports are re served, read/write '0'. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 187 - revision a2 host controller root hub status register this register is reset by the u sb r eset state. register offset address r/w description reset value hcrhststus 0xfff0_5050 r/w host controller root h ub status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved ovic lpsc 15 14 13 12 11 10 9 8 drwe reserved 7 6 5 4 3 2 1 0 reserved ovrci lops bits description [31] crwe (write) clearremotewakeupenable writing a '1' to this bit clears deviceremotewakeupenable . writing a '1' has no effect. [30:18] reserved reserved. read/write 0's [17] ovic overcurrentindicatorchange this bit is set when overcurrentindicator changes. writing a '1' clears this bit. writing a '0' has no effect. [16] lpsc ( read) localpowerstatuschange not supported. always read '0'. (write) setglobalpower write a '1' issues a setglobalpower command to the ports. writing a '0' has no effect. [15] drwe (read) deviceremotewakeupenable this bit enables ports' connects tatuschange as a remote wakeup event. 0 = disabled 1 = enabled (write) setremotewakeupenable writing a '1' sets deviceremotewakeupenable. writing a '0' has no effect. [14:2] reserved reserved. read/write 0's free datasheet http:///
W90N745cd/W90N745cdg - 188 - continued. bits description [1] ovrci overcurrentindicator this bit reflects the state of the ovrcur pin. this field is only valid if noovercurrentprotection and overcurrentprotectionmode are cleared. 0 = no over-current condition 1 = over-current condition [0] lops (read) localpowerstatus not supported. always read '0'. (write) clearglobalpower writing a '1' issues a clearglobalpower command to the ports. writing a '0' has no effect. host controller root hub port status [1][2] this register is reset by the u sb r eset state. register address r/w description reset value hcrhportstatus [1] 0xfff0_5054 r/w host controller root hub port status [1] 0x0000_0000 hcrhportstatus [2] 0xfff0_5058 r/w host controller root hub port status [2] 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved prsc pocic pssc pesc csc 15 14 13 12 11 10 9 8 reserved lsda pps 7 6 5 4 3 2 1 0 reserved spr cps sps spe drm bits description [31:21] reserved reserved. read/write 0's [20] prsc portresetstatuschange this bit indicates that the por t reset signal has completed. 0 = port reset is not complete. 1 = port reset is complete. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 189 - revision a2 continued. bits description [19] pocic portovercurrentindicatorchange this bit is set when overcurrentindicator changes. writing a '1' clears this bit. writing a '0' has no effect. [18] pssc portsuspendstatuschange this bit indicates the completion of t he selective resume sequence for the port. 0 = port is not resumed. 1 = port resume is complete. [17] pesc portenablestatuschange this bit indicates that the port has been disabled due to a hardware event (cleared portenablestatus ). 0 = port has not been disabled. 1 = portenablestatus has been cleared. [16] csc connectstatuschange this bit indicates a connect or disconnect event has been detected. writing a '1' clears this bit. writing a '0' has no effect. 0 = no connect/disconnect event. 1 = hardware detection of connect/disconnect event. note: if deviceremoveable is se t, this bit resets to '1'. [15:10] reserved reserved. read/write 0's [9] lsda (read) lowspeeddeviceattached this bit defines the speed (and bud idle) of the attached device. it is only valid when currentconnectstatus is set. 0 = full speed device 1 = low speed device (write) clearportpower writing a '1' clears portpowerstatus . writing a '0' has no effect [8] pps (read) portpowerstatus this bit reflects the power state of t he port regardless of the power switching mode. 0 = port power is off. 1 = port power is on. note: if nopowerswitching is set, this bit is always read as '1'. (write) setportpower writing a '1' sets portpowerstatus . writing a '0' has no effect. [7:5] reserved reserved. read/write 0's free datasheet http:///
W90N745cd/W90N745cdg - 190 - continued. bits description [4] spr (read) portresetstatus 0 = port reset signal is not active. 1 = port reset signal is active. (write) setportreset writing a '1' sets portresetstatus . writing a '0' has no effect. [3] cps (read) portovercurrentindicator table of none-2 supports global over-current reporting. this bit reflects the state of the ovrcur pin dedicated to this port. this field is only valid if noovercurrentprotection is cleared and overcurrentprotectionmode is set. 0 = no over-current condition 1 = over-current condition (write) clearportsuspend writing a '1' initiates the selective re sume sequence for the port. writing a '0' has no effect. [2] sps (read) portsuspendstatus 0 = port is not suspended 1 = port is selectively suspended (write) setportsuspend writing a '1' sets portsuspendstatus . writing a '0' has no effect. [1] spe (read) portenablestatus 0 = port disabled. 1 = port enabled. (write) setportenable writing a '1' sets portenablestatus . writing a '0' has no effect. [0] drm (read) currentconnectstatus 0 = no device connected. 1 = device connected. note: if deviceremoveable is set (not removable) this bit is always '1'. (write) clearportenable writing '1' a clears portenablestatus . writing a '0' has no effect. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 191 - revision a2 usb operational mode enable register this register selects which operational mode is enabl ed. bits defined as wr ite-only are read as 0's. register address r/w description reset value operationalmodeenable 0xfff0_5204 r/w usb operational mode enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved siepd 7 6 5 4 3 2 1 0 reserved ovrcur reserved dbreg bits bit description [31:9] reserved reserved . read/write 0 [8] siepd sie pipeline disable when set, waits for all usb bus ac tivity to complete prior to returning completion status to the li st processor. this is a failsafe mechanism to avoid potential probl ems with the clk_dr transition between 1.5 mhz and 12 mhz. [7:4] reserved reserved . read/write 0 [3] ovrcurp ovrcurp (over current indicator polarity) when the ovrcurp bit is clear, the ovrcur non-inverted to input into usb host controller. in contrast, when the ovrcurp bit is set, the ovrcur inverted to input into usb host controller. [2:1] reserved reserved . read/write 0 [0] dbreg data buffer region 16 when set, the size of the data buffer region is 16 bytes. otherwise, the size is 32 bytes. free datasheet http:///
W90N745cd/W90N745cdg - 192 - 6.8 usb device controller the usb controller interfaces the ahb bus and t he usb bus. the usb controller contains both the ahb master interface and ahb slave interface. cpu programs the usb controller through the ahb slave interface. for in or out transfer, the usb controller needs to write data to memory or read data from memory through the ahb master interface. the usb controller also contains the usb transceiver to interface the usb. 6.8.1 usb endpoints it consists of four endpoints, designated ep0, epa, epb and epc. each is intended for a particular use as described below: ep0: the default endpoint uses control transfer (in/ou t) to handle configuration and control functions required by the usb specification. maximum packed size is 16 bytes. epa: designed as a general endpoint. this endpoint could be programmed to be an interrupt in endpoint or an isochronous in endpoint or a bulk in endpoint or bulk out endpoint. epb: designed as a general endpoint. this endpoint could be programmed to be an interrupt in endpoint or an isochronous in endpoint or a bulk in endpoint or bulk out endpoint. epc: designed as a general endpoint. this endpoint could be programmed to be an interrupt in endpoint or an isochronous in endpoint or a bulk in endpoint or bulk out endpoint. 6.8.2 standard device request the usb controller has built-in hard-wired state machine to automatically respond to usb standard device request. it also supports to detect the cl ass and vendor requests. for get descriptor request and class or vendor command, the firm ware will control these procedures. 6.8.3 usb device register description usb control register (usb_ctl) register address r/w description reset value usb_ctl 0xfff0_6000 r/w usb control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 ccmd vcmd sie_rcv sus_tst r wu_en susp usb_rst usb_en free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 193 - revision a2 bits descriptions [31:8] reserved [7] ccmd usb class command decode control enable 0: disable, the h/w circuit does n?t need to decode usb class command. it will return a stall status when it received a usb class command. 1: enable, the h/w circuit decodes usb class command. it will assert an interrupt event when it received a usb class command. [6] vcmd usb vendor command decode enable 0: disable, the h/w circuit doesn?t need to decode usb vendor command. it will return a stall status when it received a usb vendor command. 1: enable, the h/w circuit decodes usb vendor command. it will assert an interrupt event when it received a usb vendor command. [5] sie_rcv usb sie differential rcv source 0: rcv generated by the sie 1: rcv generated by the usb transceiver [4] sus_tst usb suspend accelerate test 0: normal operation 1: usb suspend accelerate test (only for test) [3] rwu_en usb remote wake-up enable 0: disable usb remote wake-up detect 1: enable usb remote wake-up detect [2] susp usb suspend detect enable 0: disable usb suspend detect 1: enable usb suspend detect [1] usb_rst usb engine reset 0: normal operation 1: reset usb engine [0] usb_en usb engine enable 0: disable usb engine 1: enable usb engine note: set this bit to ?0?, the device is absent from host. after set this bit to ?1?, the host will detect a device attached. free datasheet http:///
W90N745cd/W90N745cdg - 194 - usb class or vendor command register (usb_cvcmd) register address r/w description reset value usb_cvcmd 0xfff0_6004 r/w usb class or vendor command register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved cvi_lg bits descriptions [31:5] reserved [4:0] cvi_lg byte length for class and vendor command and get descriptor return data packet usb interrupt enable register (usb_ie) register address r/w description reset value usb_ie 0xfff0_6008 r/w usb interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rum_clki rst_endi usb_cgi usb_bti cvsi cdii cdoi veni 7 6 5 4 3 2 1 0 clai gstri gcfgi gdevi erri rumi susi rsti free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 195 - revision a2 bits descriptions [31:16] reserved [15] rum_clki interrupt enable for resume (for clock is stopped) 0: disable 1: enable [14] rst_endi interrupt enable for usb reset end 0: disable 1: enable [13] usb_cgi interrupt enable for device configured 0: disable 1: enable note: the interrupt occurs when device configured or dis-configured. [12] usb_bti interrupt enable for usb bus transition 0: disable 1: enable [11] cvsi interrupt enable control for status phase of class or vendor command 0: disable 1: enable [10] cdii interrupt enable control for data-in of class or vendor command 0: disable 1: enable [9] cdoi interrupt enable control for data-out of class or vendor command 0: disable 1: enable [8] veni interrupt enable control for usb vendor command 0: disable 1: enable [7] clai interrupt enable control for usb class command 0: disable 1: enable [6] gstri interrupt enable control for usb get_string_descriptor command 0: disable 1: enable [5] gcfgi interrupt enable control for usb get_configuration_descriptor command 0: disable 1: enable free datasheet http:///
W90N745cd/W90N745cdg - 196 - continued. bits descriptions [4] gdevi interrupt enable control for usb get_device_descriptor command 0: disable 1: enable [3] erri interrupt enable control for usb error detect 0: disable 1: enable [2] rumi interrupt enable control for usb resume detect 0: disable 1: enable [1] susi interrupt enable control for usb suspend detect 0: disable 1: enable [0] rsti interrupt enable control for usb reset command detect 0: disable 1: enable usb interrupt status register (usb_is) register address r/w description reset value usb_is 0xfff6_000c r usb interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rum_clks rstends usb_cgs usb_bts cvss cdis cdos vens 7 6 5 4 3 2 1 0 clas gstrs gcfgs gdevs errs rums suss rsts free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 197 - revision a2 bits descriptions [31:16] reserved [15] rum_clks interrupt status for resume (for clock is stopped) 0: no interrupt generated 1: interrupt generated [14] rstends interrupt status for usb reset end 0: no interrupt generated 1: interrupt generated [13] usb_cgs interrupt status for usb device configured 0: no interrupt generated 1: interrupt generated(configured and dis-configured) [12] usb_bts interrupt status for usb bus transition 0: no interrupt generated 1: interrupt generated [11] cvss interrupt status for status p hase of class or vendor command 0: no interrupt generated 1: interrupt generated [10] cdis interrupt status for data-in of class or vendor command 0: no interrupt generated 1: interrupt generated [9] cdos interrupt status for data-out of class or vendor command 0: no interrupt generated 1: interrupt generated [8] vens interrupt status for usb vendor command 0: no interrupt generated 1: interrupt generated [7] clas interrupt status for usb class command 0: no interrupt generated 1: interrupt generated free datasheet http:///
W90N745cd/W90N745cdg - 198 - continued. bits descriptions [6] gstrs interrupt status for usb get_string_descriptor command 0: no interrupt generated 1: interrupt generated [5] gcfgs interrupt status for usb get_ configuration_descriptor command 0: no interrupt generated 1: interrupt generated [4] gdevs interrupt status for usb get_device_descriptor command 0: no interrupt generated 1: interrupt generated [3] errs interrupt status for usb error detect 0: no interrupt generated 1: interrupt generated [2] rums interrupt status for usb resume detect 0: no interrupt generated 1: interrupt generated [1] suss interrupt status for usb suspend detect 0: no interrupt generated 1: interrupt generated [0] rsts interrupt status for usb reset command detect 0: no interrupt generated 1: interrupt generated usb interrupt status clear (usb_ic) register address r/w description reset value usb_ic 0xfff6_0010 r/w usb interrupt status clear register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 199 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rum_clkc rstendc usb_cgc usb_btc cvsc cdic cdoc venc 7 6 5 4 3 2 1 0 clac gstrc gcfgc gdevc errc rumc susc rstc bits descriptions [31:16] reserved [15] rum_clkc interrupt status clear for resume (for clock is stopped) 0: no operation 1: clear interrupt status [14] rstendc interrupt status clear for usb reset end 0: no operation 1: clear interrupt status [13] usb_cgc interrupt status clear for usb device configured 0: no operation 1: clear interrupt status [12] usb_btc interrupt status clear for usb bus transition 0: no operation 1: clear interrupt status [11] cvsc interrupt status clear for status phase of class or vendor command 0: no operation 1: clear interrupt status [10] cdic interrupt status clear for data-in of class or vendor command 0: no operation 1: clear interrupt status [9] cdoc interrupt status clear for data-out of class or vendor command 0: no operation 1: clear interrupt status free datasheet http:///
W90N745cd/W90N745cdg - 200 - continued. bits descriptions [8] venc interrupt status clear for usb vendor command 0: no operation 1: clear interrupt status [7] clac interrupt status clear for usb class command 0: no operation 1: clear interrupt status [6] gstrc interrupt status clear for usb get_string_descriptor command 0: no operation 1: clear interrupt status [5] gcfgc interrupt status clear for usb ge t_configuration_descriptor command 0: no operation 1: clear interrupt status [4] gdevc interrupt status clear for usb get_device_descriptor command 0: no operation 1: clear interrupt status [3] errc interrupt status clear for usb error detect 0: no operation 1: clear interrupt status [2] rumc interrupt status clear for usb resume detect 0: no operation 1: clear interrupt status [1] susc interrupt status clear for usb suspend detect 0: no operation 1: clear interrupt status [0] rstc interrupt status clear for usb reset command detect 0: no operation 1: clear interrupt status usb interface and string register (usb_ifstr) register address r/w description reset value usb_ifstr 0xfff06014 r/w usb inte rface and string register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 201 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved str6_en str5_en 7 6 5 4 3 2 1 0 str4_en str3_en str2_en str1_e n inf4_en inf3_en inf2_en inf1_en bits descriptions [31:10] reserved [9] str6_en usb string descriptor-6 control 0: disable 1: enable [8] str5_en usb string descriptor-5 control 0: disable 1: enable [7] str4_en usb string descriptor-4 control 0: disable 1: enable [6] str3_en usb string descriptor-3 control 0: disable 1: enable [5] str2_en usb string descriptor-2 control 0: disable 1: enable [4] str1_en usb string descriptor-1 control 0: disable 1: enable free datasheet http:///
W90N745cd/W90N745cdg - 202 - continued. bits descriptions [3] inf4_en usb interface-4 control 0: disable 1: enable [2] inf3_en usb interface-3 control 0: disable 1: enable [1] inf2_en usb interface-2 control 0: disable 1: enable [0] inf1_en usb interface-1 control 0: disable 1: enable usb control transfer-out port 0 (usb_odata0) register address r/w description reset value usb_odata0 0xfff06018 r usb control transfer-out port 0 register 0x0000_0000 31 30 29 28 27 26 25 24 odata0 23 22 21 20 19 18 17 16 odata0 15 14 13 12 11 10 9 8 odata0 7 6 5 4 3 2 1 0 odata0 bits descriptions [31:0] odata0 control transfer-out data 0 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 203 - revision a2 usb control transfer-out port 1 (usb_odata1) register address r/w description reset value usb_odata1 0xfff0601c r usb contro l transfer-out port 1 register 0x0000_0000 31 30 29 28 27 26 25 24 odata1 23 22 21 20 19 18 17 16 odata1 15 14 13 12 11 10 9 8 odata1 7 6 5 4 3 2 1 0 odata1 bits descriptions [31:0] odata1 control transfer-out data 1 usb control transfer-out port 2 (usb_odata2) register address r/w description reset value usb_odata2 0xfff06020 r usb control transfer-out port 2 register 0x0000_0000 31 30 29 28 27 26 25 24 odata2 23 22 21 20 19 18 17 16 odata2 15 14 13 12 11 10 9 8 odata2 7 6 5 4 3 2 1 0 odata2 bits descriptions [31:0] odata2 control transfer-out data 2 free datasheet http:///
W90N745cd/W90N745cdg - 204 - usb control transfer-out port 3 (usb_odata3) register address r/w description reset value usb_odata3 0xfff06024 r usb control transfer-out port 3 register 0x0000_0000 31 30 29 28 27 26 25 24 odata3 23 22 21 20 19 18 17 16 odata3 15 14 13 12 11 10 9 8 odata3 7 6 5 4 3 2 1 0 odata3 bits descriptions [31:0] odata3 control transfer-out data 3 usb control transfer-in data port0 register (usb_idata0) register address r/w description reset value usb_idata0 0xfff06028 r/w usb transfer-in data port0 register 0x0000_0000 31 30 29 28 27 26 25 24 idata0 23 22 21 20 19 18 17 16 idata0 15 14 13 12 11 10 9 8 idata0 7 6 5 4 3 2 1 0 idata0 bits descriptions [31:6] idata0 control transfer-in data0 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 205 - revision a2 usb control transfer-in data port 1 register (usb_idata1) register address r/w description reset value usb_idata1 0xfff0602c r/w usb c ontrol transfer-in data port 1 0x0000_0000 31 30 29 28 27 26 25 24 idata1 23 22 21 20 19 18 17 16 idata1 15 14 13 12 11 10 9 8 idata1 7 6 5 4 3 2 1 0 idata1 bits descriptions [31:6] idata1 control transfer-in data1 usb control transfer-in data port 2 register (usb_idata2) register address r/w description reset value usb_idata2 0xfff06030 r/w usb control transfer-in data port 2 0x0000_0000 31 30 29 28 27 26 25 24 idata2 23 22 21 20 19 18 17 16 idata2 15 14 13 12 11 10 9 8 idata2 7 6 5 4 3 2 1 0 idata2 bits descriptions [31:6] idata2 control transfer-in data2 free datasheet http:///
W90N745cd/W90N745cdg - 206 - usb control transfer-in data port 3 register (usb_idata3) register address r/w description reset value usb_idata3 0xfff06034 r/w usb control transfer-in data port 3 0x0000_0000 31 30 29 28 27 26 25 24 idata3 23 22 21 20 19 18 17 16 idata3 15 14 13 12 11 10 9 8 idata3 7 6 5 4 3 2 1 0 idata3 bits descriptions [31:6] idata3 control transfer-in data3 usb sie status register (usb_sie) register address r/w description reset value usb_sie 0xfff06038 r usb sie status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved usb_dps usb_dms free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 207 - revision a2 bits descriptions [31:2] reserved [1] usb_dps usb bus d+ signal status 0: usb bus d+ signal is low 1: usb bus d+ signal is high [0] usb_dms usb bus d- signal status 0: usb bus d- signal is low 1: usb bus d- signal is high usb engine register (usb_eng) register address r/w description reset value usb_eng 0xfff0603c r/w usb engine register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved sdo_rd cv_lda cv_stl cv_dat bits descriptions [31:4] reserved [3] sdo_rd setup or bulk-out data read control 0: no operation 1: read setup or bulk-out data from usb host note: this bit will auto clear after 32 hclk [2] cv_lda usb class and vendor command last data packet control 0: no operation 1: last data packet for data input of class and vendor command note: this bit will auto clear after 32 hclk free datasheet http:///
W90N745cd/W90N745cdg - 208 - continued. bits descriptions [1] cv_stl usb class and vendor command stall control 0: no operation 1: return stall for class and vendor command note: this bit will auto clear after 32 hclk [0] cv_dat usb class and vendor command return data control 0: no operation 1: the data packet for data input of class and vendor command or get descriptor command is ready. note: this bit will auto clear after 32 hclk usb control register (usb_ctls) register address r/w description reset value usb_ctls 0xfff06040 r usb control transfer status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 conf 7 6 5 4 3 2 1 0 reserved ctlrps its descriptions [31:16] reserved [15:8] conf usb configured value [7:5] reserved [4:0] ctlrps control transfer received packet size free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 209 - revision a2 usb configured value register (usb_confd) register address r/w description reset value usb_confd 0xfff06044 r/w usb configured value register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 confd bits descriptions [31:8] reserved [7:0] confd software configured value usb endpoint a information register (epa_info) register address r/w description reset value epa_info 0xfff06048 r/w usb endpoint a information register 0x0000_0000 31 30 29 28 27 26 25 24 reserved epa_type epa_dir reserved epa_mps 23 22 21 20 19 18 17 16 epa_mps 15 14 13 12 11 10 9 8 epa_alt epa_inf 7 6 5 4 3 2 1 0 epa_cfg epa_num free datasheet http:///
W90N745cd/W90N745cdg - 210 - bits descriptions [31] reserved [30:29] epa_type endpoint a type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] epa_dir endpoint a direction 0: out 1: in [27:26] reserved [25:16] epa_mps endpoint a max. packet size [15:12] epa_alt endpoint a alternative setting (read only) [11:8] epa_inf endpoint a interface [7:4] epa_cfg endpoint a configuration [3:0] epa_num endpoint a number usb endpoint a control register (epa_ctl) register address r/w description reset value epa_ctl 0xfff0604c r/w usb endpoint a control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epa_zero epa_stl_clr epa_thre epa_stl epa_rdy epa_rst epa_en free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 211 - revision a2 bits descriptions [31:6] reserved [6] epa_zero send zero length packet to host [5] epa_stl_clr clear the endpoint a stall(write only) [4] epa_thre endpoint a threshold (only for iso) 1: once available space in fifo over 16 bytes, dma accesses memory 0: once available space in fifo over 32 bytes, dma accesses memory [3] epa_stl set the endpoint a stall [2] epa_rdy the memory is ready for endpoint a to access [1] epa_rst endpoint a reset [0] epa_en endpoint a enable usb endpoint a interrupt en able register (epa_ie) register address r/w description reset value epa_ie 0xfff06050 r/w usb endpoint a in terrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epa_cf_ie epa_bus_err_ie epa_dma_ie epa_alt_ie epa_tk_ie epa_stl_ie free datasheet http:///
W90N745cd/W90N745cdg - 212 - bits descriptions [31:6] reserved [5] epa_cf_ie endpoint a clear feature interrupt enable [4] epa_bus_err_ie endpoint a system bus error interrupt enable [3] epa_dma_ie endpoint a dma transfer complete interrupt enable [2] epa_alt_ie endpoint a alternate setting interrupt enable [1] epa_tk_ie endpoint a token input interrupt enable [0] epa_stl_ie endpoint a stall interrupt enable usb endpoint a interrupt cl ear register (epa_ic) register address r/w description reset value epa_ic 0xfff06054 w usb endpoint a interrupt clear register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epa_cf_ic epa_bus_err_ic epa_dma_ic epa_alt_ic epa_tk_ic epa_stl_ic bits descriptions [31:6] reserved [5] epa_cf_int_ic endpoint a clear feature interrupt clear [4] epa_bus_err_ic endpoint a system bus error interrupt clear [3] epa_dma_ic endpoint a dma trans fer complete interrupt clear free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 213 - revision a2 continued . bits descriptions [2] epa_alt_ic endpoint a alternate setting interrupt clear [1] epa_tk_ic endpoint a token input interrupt clear [0] epa_stl_ic endpoint a stall interrupt clear usb endpoint a interrupt st atus register (epa_is) register address r/w description reset value epa_is 0xfff06058 r usb endpoint a interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epa_cf_is epa_bus_err_is epa_dma_is epa_alt_is epa_tk_is epa_stl_is bits descriptions [31:6] reserved [5] epa_cf_is endpoint a clear feature interrupt status [4] epa_bus_err_is endpoint a syst em bus error interrupt status [3] epa_dma_is endpoint a dma trans fer complete interrupt status [2] epa_alt_is endpoint a alternative setting interrupt status [1] epa_tk_is endpoint a token interrupt status [0] epa_stl_is endpoint a stall interrupt status free datasheet http:///
W90N745cd/W90N745cdg - 214 - usb endpoint a address register (epa_addr) register address r/w description reset value epa_addr 0xfff0605c r/w usb endpoint a address register 0x0000_0000 31 30 29 28 27 26 25 24 epa_addr 23 22 21 20 19 18 17 16 epa_addr 15 14 13 12 11 10 9 8 epa_addr 7 6 5 4 3 2 1 0 epa_addr bits descriptions [31:0] epa_addr endpoint a transfer address usb endpoint a transfer le ngth register (epa_lenth) register address r/w description reset value epa_lenth 0xfff06060 r/w usb endpoint a transfer length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved epa_lenth 15 14 13 12 11 10 9 8 epa_lenth 7 6 5 4 3 2 1 0 epa_lenth free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 215 - revision a2 bits descriptions [31:20] reserved [19:0] epa_lenth endpoint a transfer length usb endpoint b information register (epb_info) register address r/w description reset value epb_info 0xfff06064 r/w usb endpoint b information register 0x0000_0000 31 30 29 28 27 26 25 24 reserved epb_type epb_dir reserved epb_mps 23 22 21 20 19 18 17 16 epb_mps 15 14 13 12 11 10 9 8 epb_alt epb_inf 7 6 5 4 3 2 1 0 epb_cfg epb_num bits descriptions [31] reserved [30:29] epb_type endpoint b type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] epb_dir endpoint b direction 0: out 1: in [27:26] reserved [25:16] epb_mps endpoint b max. packet size free datasheet http:///
W90N745cd/W90N745cdg - 216 - continued. bits descriptions [15:12] epb_alt endpoint b alternative setting (read only) [11:8] epb_inf endpoint b interface [7:4] epb_cfg endpoint b configuration [3:0] epb_num endpoint b number usb endpoint b control register (epb_ctl) register address r/w description reset value epb_ctl 0xfff06068 r/w usb endpoint b control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epb_zero epb_stl_clr epb_thre epb_stl epb_rdy epb_rst epb_en bits descriptions [31:7] reserved [6] epb_zero send zero length packet back to host [5] epb_stl_clr clear the endpoint b stall(write only) [4] epb_thre endpoint b threshold (only for iso) 1: once available space in fifo over 16 bytes, dma accesses memory 0: once available space in fifo over 32 bytes, dma accesses memory [3] epb_stl set the endpoint b stall free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 217 - revision a2 continued. bits descriptions [2] epb_rdy the memory is ready for endpoint b to access [1] epb_rst endpoint b reset [0] epb_en endpoint b enable usb endpoint b interrupt en able register (epb_ie) register address r/w description reset value epb_ie 0xfff0606c r/w usb endpoint b interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epb_cf_ie epb_bus_err_ie epb_dma_ie epb_alt_ie epb_tk_ie epb_stl_ie bits descriptions [31:6] reserved [5] epb_cf_ie endpoint b clear feature interrupt enable [4] epb_bus_err_ie endpoint b system bus error interrupt enable [3] epb_dma_ie endpoint b dma transfer complete interrupt enable [2] epb_alt_ie endpoint b alternate setting interrupt enable [1] epb_tk_ie endpoint b token input interrupt enable [0] epb_stl_ie endpoint b stall interrupt enable free datasheet http:///
W90N745cd/W90N745cdg - 218 - usb endpoint b interrupt cl ear register (epb_ic) register address r/w description reset value epb_ic 0xfff06070 w usb endpoint b interrupt clear register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epb_cf_ic epb_bus_err_ic epb_dma_ic epb_alt_ic epb_tk_ic epb_stl_ic bits descriptions [31:6] reserved [5] epb_cf_ic endpoint b clear feature interrupt clear [4] epb_bus_err_ic endpoint b system bus error interrupt clear [3] epb_dma_ic endpoint b dma trans fer complete interrupt clear [2] epb_alt_ic endpoint b alternate setting interrupt clear [1] epb_tk_ic endpoint b token input interrupt clear [0] epb_stl_ic endpoint b stall interrupt clear usb endpoint b interrupt st atus register (epb_is) register address r/w description reset value epb_is 0xfff06074 r usb endpoint b interrupt status register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 219 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epb_cf_is epb_bus_err_is epb_dma_is epb_alt_is epb_tk_is epb_stl_is bits descriptions [31:6] reserved [5] epb_cf_is endpoint b clear feature interrupt status [4] epb_dma_is endpoint b system bus error interrupt status [3] epb_dma_is endpoint b dma trans fer complete interrupt status [2] epb_alt_is endpoint b alternative setting interrupt status [1] epb_tk_is endpoint b token interrupt status [0] epb_stl_is endpoint b stall interrupt status usb endpoint b address register (epb_addr) register address r/w description reset value epb_addr 0xfff06078 r/w usb endpoint b address register 0x0000_0000 31 30 29 28 27 26 25 24 epb_addr 23 22 21 20 19 18 17 16 epb_addr 15 14 13 12 11 10 9 8 epb_addr 7 6 5 4 3 2 1 0 epb_addr free datasheet http:///
W90N745cd/W90N745cdg - 220 - bits descriptions [31:0] epb_addr endpoint b transfer address usb endpoint b transfer le ngth register (epb_lenth) register address r/w description reset value epb_lenth 0xfff0607c r/w usb endpoint b transfer length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved epb_lenth 15 14 13 12 11 10 9 8 epb_lenth 7 6 5 4 3 2 1 0 epb_lenth bits descriptions [31:20] reserved [19:0] epb_lenth endpoint b transfer length usb endpoint c information register (epc_info) register address r/w description reset value epc_info 0xfff06080 r/w usb endpoint c information register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 221 - revision a2 31 30 29 28 27 26 25 24 reserved epc_type epc_dir reserved epc_mps 23 22 21 20 19 18 17 16 epc_mps 15 14 13 12 11 10 9 8 epc_alt epc_inf 7 6 5 4 3 2 1 0 epc_cfg epc_num bits descriptions [31] reserved [30:29] epc_type endpoint c type 00: reserved 01: bulk 10: interrupt 11: isochronous [28] epc_dir endpoint c direction 0: out 1: in [27:26] reserved [25:16] epc_mps endpoint c max. packet size [15:12] epc_alt endpoint c al ternative setting (read only) [11:8] epc_inf endpoint c interface [7:4] epc_cfg endpoint c configuration [3:0] epc_num endpoint c number free datasheet http:///
W90N745cd/W90N745cdg - 222 - usb endpoint c control register (epc_ctl) register address r/w description reset value epc_ctl 0xfff06084 r/w usb endpoint c control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epc_zero epc_stl_clr epc_thre epc_stl epc_rdy epc_rst epc_en bits descriptions [31:7] reserved [6] epc_zero send zero length packet back to host [5] epc_stl_clr clear the endpoint c stall(write only) [4] epc_thre endpoint c threshold (only for iso) 1: once available space in fifo over 16 bytes, dma accesses memory 0: once available space in fifo over 32 bytes, dma accesses memory [3] epc_stl set the endpoint c stall [2] epc_rdy the memory is ready for endpoint c to access [1] epc_rst endpoint c reset [0] epc_en endpoint c enable free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 223 - revision a2 usb endpoint c interrupt en able register (epc_ie) register address r/w description reset value epc_ie 0xfff0608 8 r/w usb endpoint c interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epc_cf_ie epc_bus_err_ie epc_dma_ie epc_alt_ie epc_tk_ie epc_stl_ie bits descriptions [31:6] reserved [5] epc_cf_ie endpoint c clear feature interrupt enable [4] epc_dma_ie endpoint c system bus error interrupt enable [3] epc_dma_ie endpoint c dma transfer complete interrupt enable [2] epc_alt_ie endpoint c alternate setting interrupt enable [1] epc_tk_ie endpoint c token input interrupt enable [0] epc_stl_ie endpoint c stall interrupt enable usb endpoint c interrupt cl ear register (epc_ic) register address r/w description reset value epc_ic 0xfff0608c w usb endpoint c interrupt clear register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 224 - 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epc_cf_ic epc_bus_err_ic epc_dma_ic epc_alt_ic epc_tk_ic epc_stl_ic bits descriptions [31:6] reserved [5] epc_cf_ic endpoint c clear feature interrupt clear [4] epc_dma_ic endpoint c system bus error interrupt clear [3] epc_dma_ic endpoint c dma transfer complete interrupt clear [2] epc_alt_ic endpoint c alternate setting interrupt clear [1] epc_tk_ic endpoint c token input interrupt clear [0] epc_stl_ic endpoint c stall interrupt clear usb endpoint c interrupt st atus register (epc_is) register address r/w description reset value epc_is 0xfff06090 r usb endpoint c interrupt status register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 225 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved epc_cf_is epc_bus_err_is epc_dma_is epc_alt_is epc_tk_is epc_stl_is bits descriptions [31:6] reserved [5] epc_cf_is endpoint c clear feature interrupt status [4] epc_bus_err_is endpoint a syst em bus error interrupt status [3] epc_dma_is endpoint a dma trans fer complete interrupt status [2] epc_alt_is endpoint a alternative setting interrupt status [1] epc_tk_is endpoint a token interrupt status [0] epc_stl_is endpoint a stall status usb endpoint c address register (epc_addr) register address r/w description reset value epc_addr 0xfff0_6094 r/w usb endpoint c address register 0x0000_0000 31 30 29 28 27 26 25 24 epc_addr 23 22 21 20 19 18 17 16 epc_addr 15 14 13 12 11 10 9 8 epc_addr 7 6 5 4 3 2 1 0 epc_addr free datasheet http:///
W90N745cd/W90N745cdg - 226 - bits descriptions [31:0] epc_addr endpoint c transfer address usb endpoint c transfer le ngth register (epc_lenth) register address r/w description reset value epc_lenth 0xfff0_6098 r/w usb endpoint c transfer length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved epc_lenth 15 14 13 12 11 10 9 8 epc_lenth 7 6 5 4 3 2 1 0 epc_lenth bits descriptions [31:20] reserved [19:0] epc_lenth endpoint c transfer length usb endpoint a remain transfer length register (epa_xfer) register address r/w description reset value epa_xfer 0xfff0_609c r/w usb endpoint a remain transfer length register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 227 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved epa_xfer 15 14 13 12 11 10 9 8 epa_xfer 7 6 5 4 3 2 1 0 epa_xfer bits descriptions [31:20] reserved [19:0] epa_xfer endpoint a remain transfer length usb endpoint a remain packet length register (epa_pkt) register address r/w description reset value epa_pkt 0xfff0_60a0 r/w usb endpoint a remain packet length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved epa_pkt 7 6 5 4 3 2 1 0 epa_pkt bits descriptions [31:10] reserved [9:0] epa_pkt endpoint a remain packet length free datasheet http:///
W90N745cd/W90N745cdg - 228 - usb endpoint b remain transfer length register (epb_xfer) register address r/w description reset value epb_xfer 0xfff0_60a4 r/w usb endpoint b remain transfer length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved epb_xfer 15 14 13 12 11 10 9 8 epb_xfer 7 6 5 4 3 2 1 0 epb_xfer bits descriptions [31:20] reserved [19:0] epb_xfer endpoint b remain transfer length usb endpoint b remain packet length register (epb_pkt) register address r/w description reset value epb_pkt 0xfff0_60a8 r/w usb endpoint b remain packet length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved epb_pkt 7 6 5 4 3 2 1 0 epb_pkt free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 229 - revision a2 bits descriptions [31:10] reserved [9:0] epb_pkt endpoint b remain packet length usb endpoint c remain transfer length register (epc_xfer) register address r/w description reset value epc_xfer 0xfff0_60ac r/w usb endpoint c remain transfer length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved epc_xfer 15 14 13 12 11 10 9 8 epc_xfer 7 6 5 4 3 2 1 0 epc_xfer bits descriptions [31:20] reserved [19:0] epc_xfer endpoint c remain transfer length free datasheet http:///
W90N745cd/W90N745cdg - 230 - usb endpoint c remain packet length register (epc_pkt) register address r/w description reset value epc_pkt 0xfff0_60b0 r/w usb endpoint c remain packet length register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved epc_pkt 7 6 5 4 3 2 1 0 epc_pkt bits descriptions [31:10] reserved [9:0] epc_pkt endpoint c remain packet length free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 231 - revision a2 6.9 audio controller the audio controller consists of i2 s/ac-link protocol to interface with external audio codec. one 8-level deep fifo for read path and write path and each level has 32-bit width (16 bits for right channel and 16 bits for left channel). one dma cont roller handles the data movement between fifo and memory. the following are the property of the dma. ? always 8-beat incrementing burst ? always bus lock when 8-beat incrementing burst ? when reach middle and end address of destinati on address, a dma_irq is requested to cpu automatically an ahb master port and an ahb slave por t are offered in audio controller. 6.9.1 i2s interface the i2s interface signals are shown as figure 6.9.1 figure 6.9.1 the interface signal of i2s audio controller audio codec mclk bclk lrclk dout din free datasheet http:///
W90N745cd/W90N745cdg - 232 - the 16 bits i2s and msb-justified format are suppor t, the timing diagram is shown as figure 6.9.2 lrclk bck data left right 123 msb b2 12 lsb m sb i2s bus lrclk bck data left right 123 b2 b3 12 msb b2 m s b ?ju stified form at msb lsb figure 6.9.2 the format of i2s the sampling rate, bit shift clock frequency could be set by the control register actl_i2scon. 6.9.2 ac97 interface the ac97 interface, called ac-link is supported. fo r input and output direction, each frame contains a tag slot and 12 data slots. howe ver, in the 12 data slots, only 4 slots are used in W90N745 , other 8 slots are not supported, and the c ontrol data and audio data are transferred in the 4 valid slots. each slot contains 20 bits data. the interface signals are shown as figure 6.9.3 figure 6.9.3 the interface signal of ac-link audio controller audio codec sync bclk din dout resetb free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 233 - revision a2 the signal format is shown as figure 6.9.4 figure 6.9.4 the signal format of ac-link the structure of output frame is shown as below: slot # 0 1 2 3 4 5 6 7 8 9 10 11 12 content tag cmd addr cmd data pcm left pcm right unused bits 15-0 19-0 19-0 19-0 19-0 159 - 0 phase tag phase data phase the output frame data format is shown as following: slot # bit description 15 frame validity bit, 1 is valid, 0 is invalid. 14 - 3 slot validity, but in W90N745, only bits 6-3 are used, bits 14-7 are unused. bit 3 is corresponding to slot 1, bit 4 is corresponding to slot 2, etc.. 1 is valid, 0 is invalid . the unused bits 14-7 should be cleared to 0. tag (slot 0) 2 - 0 this field should be cleared to 0. 19 read/write control, 1 for read and 0 for write 18-12 control register address cmd addr (slot 1) 11 - 0 this field should be cleared to 0 . . . . . . . . . . . . . . . . . . syn bcl din dou tag phase data phase s lot 0 slot 1 slot 2 slot 3 slot 4 slot 5 ?12 frame (48 khz) 12.2 88 mhz b255 b0 b1 b15 b16 b35 ms ls b36 b55 b56 b75 b76 b95 b96 b255 free datasheet http:///
W90N745cd/W90N745cdg - 234 - continued. slot # bit description 19 - 4 control register write data. it should be cleared to 0 if current operation is read. cmd data (slot 2) 3 - 0 this field should be cleared to 0 19 - 4 pcm playback data for left channel pcm left (slot 3) 3 - 0 this field should be cleared to 0 19 - 4 pcm playback data for right channel pcm right (slot 4) 3 - 0 this field should be cleared to 0 the structure of input frame is shown as below: slot # 0 1 2 3 4 5 6 7 8 9 10 11 12 content tag status addr status data pcm left pcm right unused bits 0-15 19-0 19-0 19-0 19-0 159 - 0 the input frame data format is shown as following: slot # bit description 15 frame validity bit, 1 is valid, 0 is invalid. 14 - 3 slot validity, but in W90N745, only bits 6-3 are used, bits 14-7 are unused. bit 3 is corresponding to slot 1, bit 4 is corresponding to slot 2, etc.. 1 is valid, 0 is invalid . the unused bits 14-7 should be cleared to 0. tag (slot 0) 2 - 0 this field should be cleared to 0. 19 this bit should be cleared to 0 18-12 control register address echo which previous frame requested 11 pcm data for left channel request, it should be always 0 when vra=0 (vra: variable rate audio mode). 10 pcm data for right channel request (same as bit 11). status addr (slot 1) 9 - 0 this field should be cleared to 0 19 - 4 control register read data which pr evious frame requested. it should be cleared to 0 if this slot is invalid. status data (slot 2) 3 - 0 this field should be cleared to 0 19 - 4 pcm record data for left channel pcm left (slot 3) 3 - 0 this field should be cleared to 0 19 - 4 pcm record data for right channel pcm right (slot 4) 3 -0 this field should be cleared to 0 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 235 - revision a2 6.9.3 audio controller register map r : read only, w : write only, r/w : both read and write, c : only value 0 can be written register address r/w description reset value actl_con 0xfff0_9000 r/w audio controlle r control register 0x0000_0000 actl_reset 0xfff0_9004 r/w sub block rese t control register 0x0000_0000 actl_rdstb 0xfff0_9008 r/w dma destination base address register for record 0x0000_0000 a ctl _ rdst_length 0xfff0_900c r/w dma destination length register for record 0x0000_0000 actl_rdstc 0xfff0_9010 r dma destination current address register for record 0x0000_0000 actl_rsr 0xfff0_9014 r/w record stat us register 0x0000_0000 actl_pdstb 0xfff0_9018 r/w dma destination base address register for play 0x0000_0000 a ctl _ pdst_length 0xfff0_901c r/w dma destination length register for play 0x0000_0000 actl_pdstc 0xfff0_9020 r dma destination current address register for play 0x0000_0000 actl_psr 0xfff0_9024 r/w play status register 0x0000_0004 actl_i 2 scon 0xfff0_9028 r/w i2s control register 0x0000_0000 actl_accon 0xfff0_902c r/w ac-link control register 0x0000_0000 actl_acos0 0xfff0_9030 r/w ac-link out slot 0 0x0000_0000 actl_acos1 0xfff0_9034 r/w ac-link out slot 1 0x0000_0080 actl_acos2 0xfff0_9038 r/w ac-link out slot 2 0x0000_0000 actl_acis0 0xfff0_903c r ac-link in slot 0 0x0000_0000 actl_acis1 0xfff0_9040 r ac-link in slot 1 0x0000_0000 actl_acis2 0xfff0_9044 r ac-link in slot 2 0x0000_0000 audio controller control registers (actl_con) register address r/w description reset value actl_con 0xfff0_9000 r/w audio contro ller control register 0x0000_0000 the actl_con register control the basic operation of audio controller. free datasheet http:///
W90N745cd/W90N745cdg - 236 - bits descriptions [15] reserved - [14] reserved - [13] reserved - [12] r_dma_irq when recording, when the dma destinat ion current address reach the dma destination end address or middle address, the r_dma_irq bit will be set to 1 automatically, and this bit could be cleared to 0 by cpu. the bit is hardwired to arm as interrupt request signal with an inverter. the r_dma_irq bit is read/write ( write 1 to clear ) [11] t_dma_irq transmit dma interrupt request bit. when dma current address reach the middle address (((actl_dese ? actl_desb)-1)/2 + actl_desb) or reach the end address actl_desb, the bi t t_dma_irq will be set to 1, and this bit could be clear to 0 by write ?1 ? by cpu. and the bit is hardwired to arm as interrupt request signal with an inverter. the t_dma_irq bit is read/write ( write 1 to clear ). [8] i2s_ac_pin_sel i 2 s or ac-link pin selection ? if i 2 s_ac_pin_sel = 0, the pins select i 2 s ? if i 2 s_ac_pin_sel = 1, the pins select ac-link the i 2 s_ac_pin_sel bis is read/write [7] fifo_th fifo threshold control bit ? if fifo_th=0, the fifo threshold is 8 level ? if fifo_th=1, the fifo threshold is 4 level the fifo_th bit is read/write [6] reserved [2:1] block_en[1:0] audio interface type selection ? if block_en[0]=0/1, i 2 s interface is disable/enable ? if block_en[1]=0/1, ac-link interface is disable/enable the block_en[1:0] bits are read/write [0] reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 reserved reserved reserved r_dma_irq t_dma_irq reserved i 2 s_ac_pin_sel 7 6 5 4 3 2 1 0 fifo_th reserved reserved block_en[1:0] reserved free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 237 - revision a2 sub-block reset control register (actl_reset) register address r/w description reset value actl_reset 0xfff0_9004 r/w sub block reset control 0x0000_0000 the value in actl_reset register contro l the reset operation in each sub block. bits descriptions [31:17] reserved - [16] actl_reset audio controller reset control bit 1 = the whole audio controller is reset 0 = the audio controller is normal operation the actl_reset bit is read/write [15:14] record_single [1:0] record single/dual channel select bits 2?b11= the record is dual channel 2?b01= the record only select left channel 2?b10= the record only select right channel 2?b00 is reserved note that, when adc is selected as record path, it only support left channel record. the play_single[1:0] bits are read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 actl_reset 15 14 13 12 11 10 9 8 record_single[1:0] play_single[1:0] reserved ac_recor d 7 6 5 4 3 2 1 0 ac_play i 2 s_record i 2 s_play reserved ac_reset i 2 s_reset free datasheet http:///
W90N745cd/W90N745cdg - 238 - continued. bits descriptions [13:12] play_single [1:0] playback single/dual channel select bits play_single[1:0]=11, the playback is in stereo mode play_single[1:0]=10, the playback is in mono mode play_single[1:0]= 00 & 01 is reserved the play_single[1:0] bits are read/write [8] ac_record ac link record control bit ac_record=0, the record path of ac link is disable ac_record=1, the record path of ac link is enable the ac_record bit is read/write [7] ac_play ac link playback control bit ac_play=0, the playback path of ac link is disable ac_play=1, the playback path of ac link is enable the ac_play bit is read/write [6] i 2 s_record i 2 s record control bit i 2 s_record=0, the record path of i 2 s is disable i 2 s_record=1, the record path of i 2 s is enable the i2s_record bit is read/write [5] i 2 s_play i 2 s playback control bit i 2 s_play=0, the playback path of i 2 s is disable i 2 s_play=1, the playback path of i 2 s is enable the i2s_play bit is read/write [1] ac_reset ac link sub block reset control bit ac_reset=0, release the ac link function block from reset mode ac_reset=1, force the ac link function block to reset mode the ac_reset bit is read/write [0] i 2 s_reset i 2 s sub block reset control bit i 2 s_reset=0, release the i 2 s function block from reset mode i 2 s_reset=1, force the i 2 s function block to reset mode the i2s_reset bit is read/write dma record destination base address (actl_rdstb) register address r/w description reset value actl_rdstb 0xfff0_9008 r/w dma record destination base address 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 239 - revision a2 the value in actl_rdstb register is the reco rd destination base address of dma, and only could be changed by cpu. bits descriptions [31:0] audio_rdstb[31:0] 32-bit record destination base address the audio_rdstb[31:0] bits is read/write. dma destination end address (actl_rdst_length) register address r/w description reset value actl_rdst_length 0xfff0_900c r/w dma record des tination address length 0x0000_0000 the value in actl_rdst_length register is t he record destination address length of dma, and the register could only be changed by cpu. 31 30 29 28 27 26 25 24 audio_rdstb[31:24] 23 22 21 20 19 18 17 16 audio_rdstb[23:16] 15 14 13 12 11 10 9 8 audio_rdstb[15:8] 7 6 5 4 3 2 1 0 audio_rdstb[7:0] 31 30 29 28 27 26 25 24 audio_rdst_l[31:24] 23 22 21 20 19 18 17 16 audio_rdst_l[23:16] 15 14 13 12 11 10 9 8 audio_rdst_l[15:8] 7 6 5 4 3 2 1 0 audio_rdst_l[7:0] free datasheet http:///
W90N745cd/W90N745cdg - 240 - bits descriptions [31:0] audio_rdst_l[31:0] 32-bit record destination address length the audio_rdst_l[31:0] bits is read/write. dma destination current address (actl_rdstc) register address r/w description reset value actl_rdstc 0xfff0_9010 ro dma record destination current address 0x0000_0000 the value in actl_rdstc is the dma record desti nation current address, this register could only be read by cpu. bits descriptions [31:0] audio_rdstc[31:0] 32-bit record destination current address the audio_rdstc[31:0] bits is read only. audio controller record status register (actl_rsr) register address r/w description reset value actl_rsr 0xfff0_9014 r/w audio controller fifo and dma status register for record 0x0000_0000 31 30 29 28 27 26 25 24 audio_rdstc[31:24] 23 22 21 20 19 18 17 16 audio_rdstc[23:16] 15 14 13 12 11 10 9 8 audio_rdstc[15:8] 7 6 5 4 3 2 1 0 audio_rdstc[7:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 241 - revision a2 bits descriptions [31:3] reserved - [2] r_fifo_full record fifo full indicator bit r_fifo_full=0, the record fifo not full r_fifo_full=1, the record fifo is full the r_fifo_ready bit is read only [1] r_dma_end_irq dma end address interrupt request bit for record r_dma_end_irq=0, means record dma address does not reach the end address r_dma_end_irq=1, means record dma address reach the end address the r_dma_end_irq bit is readable, and only can be clear by write ?1? to this bit [0] r_dma_middle _irq dma address interrupt request bit for record r_dma_middle_irq=0, means record dma address does not reach the middle address r_dma_middle_irq=1, means record dma address reach the middle address the r_dma_middle_irq bit is readable, and only can be clear by write ?1? to this bit dma play destination base address (actl_pdstb) register address r/w description reset value actl_pdstb 0xfff0_9018 r/w dma play des tination base address 0x0000_0000 the value in actl_pdstb register is the play destination base address of dma, and only could be changed by cpu. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved r_fifo_full r_dma_end_irq r_dma_middle_irq free datasheet http:///
W90N745cd/W90N745cdg - 242 - bits descriptions [31:0] audio_pdstb[31:0] 32-bit play destination base address the audio_pdstb[31:0] bits is read/write. dma destination end address (actl_pdst_length) register address r/w description reset value actl_pdst_length 0xfff0_901c r/w dma play desti nation address length 0x0000_0000 the value in actl_pdst_length register is t he play destination address length of dma, and the register could only be changed by cpu. 31 30 29 28 27 26 25 24 audio_pdstb[31:24] 23 22 21 20 19 18 17 16 audio_pdstb[23:16] 15 14 13 12 11 10 9 8 audio_pdstb[15:8] 7 6 5 4 3 2 1 0 audio_pdstb[7:0] 31 30 29 28 27 26 25 24 audio_pdst_l[31:24] 23 22 21 20 19 18 17 16 audio_pdst_l[23:16] 15 14 13 12 11 10 9 8 audio_pdst_l[15:8] 7 6 5 4 3 2 1 0 audio_pdst_l[7:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 243 - revision a2 bits descriptions [31:0] audio_pdst_l[31:0] 32-bit play destination address length the audio_pdst_l[31:0] bits is read/write. dma destination current address (actl_pdstc) register address r/w description reset value actl_pdstc 0xfff0_9020 ro dma play destination current address 0x0000_0000 the value in actl_pdstc is the dma play destinat ion current address, this register could only be read by cpu. bits descriptions [31:0] audio_pdstc[31:0] 32-bit play destination current address the audio_pdstc[31:0] bits is read/write. audio controller playback status register (actl_psr) register address r/w description reset value actl_psr 0xfff0_9024 r/w audio controller fifo and dma status register for playback 0x0000_0004 31 30 29 28 27 26 25 24 audio_pdstc[31:24] 23 22 21 20 19 18 17 16 audio_pdstc[23:16] 15 14 13 12 11 10 9 8 audio_pdstc[15:8] 7 6 5 4 3 2 1 0 audio_pdstc[7:0] free datasheet http:///
W90N745cd/W90N745cdg - 244 - bits descriptions [31:3] reserved - [2] p_fifo_empty playback fifo empty indicator bit p_fifo_empty=0, the playback fifo is not empty p_fifo_empty=1, the playback fifo is empty the p_fifo_empty bit is read only [1] p_dma_end_irq dma end address interrupt request bit for playback p_dma_end_irq=0, means playback dma address does not reach the end address p_dma_end_irq=1, means playback dma address reach the end address the p_dma_end_irq bit is readable, and only can be clear by write ?1? to this bit [0] p_dma_middle_irq dma address interrupt request bit for playback p_dma_middle_irq=0, means playback dma address does not reach the middle address p_dma_middle_irq=1, means playback dma address reach the middle address the p_dma_middle_irq bit is readable, and only can be clear by write ?1? to this bit i 2 s control register (actl_i 2 scon) register address r/w description reset value actl_i 2 scon 0xfff0_9028 r/w i2s control register 0x0000_0000 the actl_i2scon is the i2s bas ic operation control register. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved p_fifo_empty p_dma_end_irq p_dma_middle_irq free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 245 - revision a2 bits descriptions [31:20] reserved - [19:16] prs[3:0] i2s frequency pre-scaler selection bits. (fpll is the input pll frequency, mclk is the output main clock) psr[3:0]=0000, mclk=fpll/1 psr[3:0]=0001, mclk=fpll/2 psr[3:0]=0010, mclk=fpll/3 psr[3:0]=0011, mclk=fpll/4 psr[3:0]=0100, mclk=fpll/5 psr[3:0]=0101, mclk=fpll/6 psr[3:0]=0110, mclk=fpll/7 psr[3:0]=0111, mclk=fpll/8 psr[3:0]=1000, reserved psr[3:0]=1001, mclk=fpll/10 psr[3:0]=1010, reserved psr[3:0]=1011, mclk=fpll/12 psr[3:0]=1100, reserved psr[3:0]=1101, mclk=fpll/14 psr[3:0]=1110, reserved psr[3:0]=1111, mclk=fpll/16 (when the division factor is 3/5/7, the duty cycle of mclk is not 50%, the high duration is 0.5*fpll) the psr[3:0] bits are read/write 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved prs[3:0] 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 bclk_sel[1:0] fs_sel mclk_sel format reserved free datasheet http:///
W90N745cd/W90N745cdg - 246 - continued bits descriptions [7:6] bclk_sel [1:0] i2s serial data clock frequency selection bit bclk_sel[1:0]=00, 32fs is selected (fs is sampling rate), when fs_sel=0, the frequency of bit clock is mclk/8, when fs_sel=1, the frequency of bit clock is mclk/12. bclk_sel[1:0]=01, 48fs is sele cted (only when fs_sel=1, this term could be selection), when fs_sel=1, the frequency of bit clock is mclk/8. the bclk_sel[1:0] bits are read/write [5] fs_sel i2s sampling frequency selection bit fs_sel=0, fmclk/256 is selected (fmclk is the frequency of signal mclk) fs_sel=1, fmclk/384 is selected the fs_sel bit is read/write [4] mclk_sel i2s mclk output selection bit mclk_sel=0, i 2 s mclk output will follow the prs[3:0] setting. mclk_sel=1, i 2 s mclk output will be the same with fpll. the mclk_sel bit is read/write [3] format i2s format selection bits format=0, i 2 s compatible format is selected format=1, msb-justified format is selected the format bit is read/write [2:0] reserved - ac-link control register (actl_accon) register address r/w description reset value actl_accon 0xfff0_902c r/w ac-link control register 0x0000_0000 the actl_accon register is the ac- link basic operation control register. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 247 - revision a2 bits descriptions [6] reserved - [5] ac_bclk_pu_en this bit controls the ac_bclk pin pull-high resister. ac_bclk_pu_en=0, the ac_bclk pin pull-high resister will be disabled ac_bclk_pu_en=1, the ac_bclk pin pull-high resister will be enabled the ac_bclk_pu_en bit is read/write. [4] ac_r_finish ac-link read data ready bit. when read data indexed by previous frame is shifted into actl_aci s2, the ac_r_finish bit will be set to 1 automatically. afte r cpu read out the read data, ac_r_finish bit will be cleared to 0. ac_r_finish=0, read data buffer has been read by cpu ac_r_finish=1, read data buffer is ready for cpu read the ac_r_finish bit is read only [3] ac_w_finish ac-link write frame finish bit. when writing data to register actl_acos0, the ac_w_finish bit will be set to 1 automatically. after ac-link inte rface shift out the register actl_acos0, the ac_w_finish bit will be cleared to 0. ac_w_finish=0, ac-link contro l data out buffer has been shifted out to codec by cpu and data out buffer is empty. ac_w_finish=1, ac-link control data out buffer is ready to be shifted out(after users have wrote data into register actl_acos0) the ac_w_finish bit is read only 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ac_bclk_pu_en ac_r_finish ac_w_finish ac_w_res ac_c_res reserved free datasheet http:///
W90N745cd/W90N745cdg - 248 - continued. bits descriptions [2] ac_w_res ac-link warm reset control bit, when this bit is set to 1, (ac-link begin warn reset procedure, after warn reset procedure finished, this bit will be cleared automatically) the interface signal ac_sync is high, when this bit is set to 0, the interface signal ac_sync is controlled by ac_bcl k input when this bit is set to 1. note the ac-link spec. s hows it need at least 10 us high duration of ac_sync to warn reset ac97. ac_w_res=0, ac_sync pin is c ontrolled by ac_bclk input pin ac_w_res=1, ac_sync pin is forced to high the ac_w_res bit is read/write [1] ac_c_res ac-link cold reset control bit, when th is bit is set to 1, the interface signal ac_resetb is low, when this bit is set to 0, the signal ac_resetb is high. note the ac -link spec. shows it need at least 10 us low duration of ac_resetb to cold reset ac97. ac_c_res=0, ac_resetb pin is set to 1 ac_c_res=1, ac_resetb pin is set to 0 the ac_c_res bit is read/write [0] reserved - ac-link output slot 0 (actl_acos0) register address r/w description reset value actl_acos0 0xfff0_9030 r/w ac-link out slot 0 0x0000_0000 the actl_acos0 register store the slot 0 value to be shift out by ac-link. note that write data to actl_acos0 register when ac_w_finish bit (a ctl_accon[3]) is set is invalid. therefore, check ac_w_finish bit status before write data into actl_acos0 register. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved valid_ frame slot_valid[3:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 249 - revision a2 bits descriptions [31:5] reserved - [4] valid_frame frame valid indicated bits valid_frame=1, any one of slot is valid valid_frame=0, no any slot is valid the valid_frame bits are read/write [3:0] slot_valid [3:0] slot valid indicated bits slot_valid[0]= 1/0, indicate slot 1 valid/invalid slot_valid[1]= 1/0, indicate slot 2 valid/invalid slot_valid[2]= 1/0, indicate slot 3 valid/invalid slot_valid[3]= 1/0, indicate slot 4 valid/invalid the slot_valid[3:0] bits are read/write the ac-link output slot 1 (actl_acos1) register address r/w description reset value actl_acos1 0xfff0_9034 r/w ac-link out slot 1 0x0000_0080 the actl_acos1 register store the slot 1 value to be shift out by ac-link. 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 r_wb r_index[6:0] free datasheet http:///
W90N745cd/W90N745cdg - 250 - bits descriptions [31:8] reserved - [7] r_wb read/write select bit r_wb=1, a read specified by r_ index[6:0] will occur, and the data will appear in next frame r_wb=0, a write specified by r_ index[6:0] will occur, and the write data is put at out slot 2 the r_wb bit is read/write [6:0] r_index[6:0] external ac97 codec control register index (address) bits the r_index[6:0] bits are read/write ac-link output slot 2 (actl_acos2) register address r/w description reset value actl_acos2 0xfff0_9038 r/w ac-link out slot 2 0x0000_0000 the actl_acos2 register store the slot 2 value to be shift out by ac-link. bits descriptions [31:0] reserved - [15:0] wd[15:0] ac-link write data the wd[15:0] bits are read/write 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 wd[15:8] 7 6 5 4 3 2 1 0 wd[7:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 251 - revision a2 ac-link input slot 0 (actl_acis0) register address r/w description reset value actl_acis0 0xfff0_903c r ac-link in slot 0 0x0000_0000 the actl_acis0 store the shift in slot 0 data of ac-link. bits descriptions [31:5] reserved - [4] codec_ready external ac97 audio codec ready bit codec_ready=0, indicate external ac97 audio codec is not ready codec_ready=1, indicate external ac97 audio codec is ready the codec_ready bit is read only [3:0] slot_valid[3:0] slot valid indicated bits slot_valid[0]= 1/0, indicate slot 1 valid/invalid slot_valid[1]= 1/0, indicate slot 2 valid/invalid slot_valid[2]= 1/0, indicate slot 3 valid/invalid slot_valid[3]= 1/0, indicate slot 4 valid/invalid the slot_valid[3:0] bits are read 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved codec_ready slot_valid[3:0] free datasheet http:///
W90N745cd/W90N745cdg - 252 - ac-link input slot 1 (actl_acis1) register address r/w description reset value actl_acis1 0xfff0_9040 r ac-link in slot 1 0x0000_0000 the actl_acis1 stores the shift in slot 1 data of ac-link. bits descriptions [31:9] reserved - [8:2] r_index[6:0] register index. the r_index[6:0] echo the register index (address) when a register read has been request ed in the previous frame. the r_index[6:0] bits are read only [1:0] slot_req[1:0] slot request. the bits indicate if the external codec need new pcm data that will transfer in next frame. any bit in slot_req[1:0] is set to 1, indicate external codec does not need a new sample in the corresponding slot[3:4] of the next frame any slot_req[1:0] is clear to 0, indicate external codec need a new sample in the corresponding slot[3:4] of the next frame the slot_req[1:0] bits are read only 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved r_index[6] 7 6 5 4 3 2 1 0 r_index[5:0] slot_req[1:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 253 - revision a2 ac-link input slot 2 (actl_acis2) register address r/w description reset value actl_acis2 0xfff0_9044 r ac-link in slot 2 0x0000_0000 the actl_acis2 stores the shift in slot 2 data of ac-link. bits descriptions [31:16] reserved - [15:0] rd[15:0] ac-link read data. the rd[15:0] bits are read only 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 rd[15:8] 7 6 5 4 3 2 1 0 rd[7:0] free datasheet http:///
W90N745cd/W90N745cdg - 254 - 6.10 universal asynchronous receiver/transmitter controller asynchronous serial communication block include 4 uart blocks and accessory logic. they can be described as follow: ? uart0 it is merely a general purpose uart. it does not include any accessory function. clock source : 15mhz uart type : general uart fifo number : 16-byte receiving fifo and 16 byte transmitting fifo modem function : n/a accessory function : n/a ? uart1 it is designed for general purpose uart or bl uetooth transceiver. it includes a high speed uart block with 64-byte receiving fifo and 64-byte transmitting fifo. it includes 5 clock sources: 15m, 30m, 43.6m, 48m and 60m. programmer can feel free to choose the clock source and divisor number for suitable baud rate. clock source : 15mhz from external crystal 30m, 43.6m, 48m, 60m (optional function for bluetooth hci transport layer) uart type : high speed uart fifo number : 64-byte receiving fifo and 64 byte transmitting fifo modem function : cts and rts (optional for bluetooth. if they were enabled, tx & rx in uart2 will be cut off) accessory function : bluetooth (optional) baud rate (max) : 1.875mhz i/o pin : txd1, rxd1, rts, cts (optional) ? uart2 it is designed for general purpose uart or irda sir. the part of uart includes 16-byte receiving fifo and 16-byte transmitting fifo . txd2/rxd2 of uart2 occupy the same pins with rts and cts of uart1. once the bluetooth function has been enabled, uart2 should be disabled. clock source : 15mhz uart type : general uart free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 255 - revision a2 fifo number : 16-byte receiving fifo and 16 byte transmitting fifo modem function : n/a accessory function : irda sir (optional) i/o pin : txd2, rxd2. i/o pin share with : uart1 (bluetooth function) ? uart3 it is also merely a general purpose uart. it does not include any accessory function. it share four i/o pins with ac97/i2s. clock source : 15mhz uart type : general uart fifo number : 16- byte receiving fifo and 16 byte transmitting fifo modem function : dtr, dsr accessory function : n/a i/o pin : txd3, rxd3, dtr, dsr i/o pin share with : ac 97_datao, ac97_datai, ac97_sync, ac97_bitclk table 6.10.1 W90N745 uart features list block number uart type clock source modem function signals io pins design target 0 general uart 15m n/a txd0, rxd0 general uart 1 high speed uart 15m, 30m, 43.6m, 48m, 60m cts, rts txd1, rxd1, cts1, rts1 general uart/ bluetooth 2 general uart 15m n/a tx2, rx2 general uart/irda sir 3 general uart 15m dtr, dsr txd3, rxd3, drt3, dsr3 general uart free datasheet http:///
W90N745cd/W90N745cdg - 256 - 6.10.1 uart0 uart0 is a general uart block. it is same as t he uart in w90n740 but without modem i/o signals. more detail function description, please refer to section 7.10.5 general uartcontroller description table 6.10.2 uart0 register map register address r/w other condition reset value uart0_rbr 0xfff8_0000 r dlab=0 undefined uart0_thr 0xfff8_0000 w dlab=0 undefined uart0_ier 0xfff8_0004 r/w dlab=0 0x0000_0000 uart0_dll 0xfff8_0000 r/w dlab=1 0x0000_0000 uart0_dlm 0xfff8_0004 r/w dlab=1 0x0000_0000 uart0_iir 0xfff8_0008 r 0x8181_8181 uart0_fcr 0xfff8_0008 w undefined uart0_lcr 0xfff8_000c r/w 0x0000_0000 reserved 0xfff8_0010 uart0_lsr 0xfff8_0014 r 0x6060_6060 reserved 0xfff8_0018 uart0_tor 0xfff8_001c r/w 0x0000_0000 6.10.2 uart1 the uart1 is designed for general purpose uart or bluetooth hci transport layer. it is a high speed uart with 64-byte receive fifo and 64-byte transmit fifo. to perform 1.875mhz maximum baud rate, uart1 has 5 clock sources, 15m, 30m, 43.6m , 48m, and 60m. the first one is from external 15m crystal clock and the other are divided from system pll 480mhz output. more detail about high speed uart, please refer to next section 7.10.6 high speed uart controller function description. the block uart1 offer 4 i/o signals, tx, rx, cts, and rts. cts and rts are used as flow control for bluetooth. cts and rts share the same i/o pins with tx and rx in block uart2. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 257 - revision a2 table 6.10.3 uart1 register map register address r/w other condition reset value uart1_rbr 0xfff8_0100 r dlab=0 undefined uart1_thr 0xfff8_0100 w dlab=0 undefined uart1_ier 0xfff8_0104 r/w dlab=0 0x0000_0000 uart1_dll 0xfff8_0100 r/w dlab=1 0x0000_0000 uart1_dlm 0xfff8_0104 r/w dlab=1 0x0000_0000 uart1_iir 0xfff8_0108 r 0x8181_8181 uart1_fcr 0xfff8_0108 w undefined uart1_lcr 0xfff8_010c r/w 0x0000_0000 uart1_mcr 0xfff8_0110 r/w 0x0000_0000 uart1_lsr 0xfff8_0114 r 0x6060_6060 uart1_msr 0xfff8_0118 r 0x0000_0000 uart1_tor 0xfff8_011c r/w 0x0000_0000 uart1_ubcr 0xfff8_0120 r/w 0x0000_0000 uart1 bluetooth control register (uart1_ubcr) register address r/w description reset value uart1_ubcr 0xfff8_0120 r/w uart 1 bluetooth control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ubcr[2:0] free datasheet http:///
W90N745cd/W90N745cdg - 258 - bits descriptions [31:3] reserved - [2:0] ubcr ubcr is a 3 bits register which is used to select clock source to generate suitable baud rate: 000: 15mhz from external crystal 100: 30mhz divided from pll 480mhz 101: 43.6mhz divided from pll 480mhz 110: 48mhz divided from pll 480mhz 111: 60mhz divided from pll 480mhz 6.10.3 uart2 uart2 contains 2 features: general uart and ir da sir decoder/encoder. uart is same as the uart of w90n740 but without modem function. please read the spec of section 7.10.5 general uart controller function description . the irda sir is described as follow: table 6.10.4 uart2 register map register address r/w other condition reset value uart2_rbr 0xfff8_0200 r dlab=0 undefined uart2_thr 0xfff8_0200 w dlab=0 undefined uart2_ier 0xfff8_0204 r/w dlab=0 0x0000_0000 uart2_dll 0xfff8_0200 r/w dlab=1 0x0000_0000 uart2_dlm 0xfff8_0204 r/w dlab=1 0x0000_0000 uart2_iir 0xfff8_0208 r 0x8181_8181 uart2_fcr 0xfff8_0208 w undefined uart2_lcr 0xfff8_020c r/w 0x0000_0000 reserved 0xfff8_0210 undefined uart2_lsr 0xfff8_0214 r 0x6060_6060 reserved 0xfff8_0218 undefined uart2_tor 0xfff8_021c r/w 0x0000_0000 uart2_ircr 0xfff8_0220 r/w 0x0000_0040 uart2 irda control register (uart2_ircr) register address r/w description reset value uart2_ircr 0xfff8_0220 r/w uart 2 irda control register 0x0000_0040 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 259 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved inv_rx inv_tx reserved reserved lb tx_select irda_en bits descriptions [31:7] reserved reserved [6] inv_rx 1: inverse rx input signal 0: no inversion [5] inv_tx 1: inverse tx output signal 0: no inversion [4:3] reserved reserved [2] lb irda loop back mode for self test. 1: enable irda loop back mode 0: disable irda loop back mode [1] tx_select 1: enable irda transmitter 0: enable irda receiver [0] irda_en 1: enable irda block 0: disable irda block free datasheet http:///
W90N745cd/W90N745cdg - 260 - 6.10.4 uart3 uart3 is a general uart block. it is same as the uart in w90n740 but with some modem i/o signals. more detail general uart function description, pl ease refer to next section 7.10.5 general uart controller. table 6.10.5 uart3 register map register address r/w other condition reset value uart3_rbr 0xfff8_0300 r dlab=0 undefined uart3_thr 0xfff8_0300 w dlab=0 undefined uart3_ier 0xfff8_0304 r/w dlab=0 0x0000_0000 uart3_dll 0xfff8_0300 r/w dlab=1 0x0000_0000 uart3_dlm 0xfff8_0304 r/w dlab=1 0x0000_0000 uart3_iir 0xfff8_0308 r 0x8181_8181 uart3_fcr 0xfff8_0308 w undefined uart3_lcr 0xfff8_030c r/w 0x0000_0000 uart3_mcr 0xfff8_0310 r/w 0x0000_0000 uart3_lsr 0xfff8_0314 r 0x6060_6060 uart3_msr 0xfff8_0318 r 0x0000_0000 uart3_tor 0xfff8_031c r/w 0x0000_0000 uart3 modem control register (uart3_mcr) register address r/w description reset value uart3_mcr 0xfff8_0310 r/w uart 3 modem control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved reserved reserved lbme reserved reserved reserved dtr# note : uart3_mcr is subset of mcr in W90N745. please refer to section 7.10.5 ?general uart controller?. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 261 - revision a2 uart3 modem status register (uart3_msr) register address r/w description reset value uart3_msr 0xfff8_0318 r uart 3 modem status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved reserved dsr# reserved reserved reserved ddsr reserved note : uart3_msr is subset of msr in W90N745. please refer to section 7.10.5 ?general uart controller?. 6.10.5 general uart controller the universal asynchronous receiver/transmitter (uart) performs a serial-to-parallel conversion on data characters received from the peripheral such as modem, and a parallel-to-serial conversion on data characters received from the cpu. t here are five types of interrupts, i.e., line status interrupt, transmitter fifo empty interrupt, receiver thres hold level reaching interrupt, time out interrupt, and modem status interrupt. one 16-byte transmitter fifo (tx_fifo) and one 16-byte (plus 3-bit of error data per byte) receiver fifo (rx_fifo) has been built in to reduce the number of interrupts presented to the cpu. the cpu can completely read the status of the uart at any time during the operation. the reported status in formation includes the type and condi tion of the transfer operations being performed by the uart, as well as any error c onditions (parity, overrun, framing, or break interrupt) found. the uart includes a programmabl e baud rate generator that is capable of dividing crystal clock input by divisors to produce the cl ock that transmitter and receiver needed. the equation is baudout = crystal clock / 16 * [divisor + 2]. the uart includes the following features: y transmitter and receiver are buffered with a 16-byte fifo each to reduce the number of interrupts presented to the cpu. y subset of modem control functions (dsr, dtr, by ip selection) y fully programmable serial-interface characteristics: -- 5-, 6-, 7-, or 8-bit character -- even, odd, or no-parity bit generation and detection -- 1-, 1&1/2, or 2-stop bit generation -- baud rate generation free datasheet http:///
W90N745cd/W90N745cdg - 262 - y line break generation and detection y false start bit detection y full prioritized interrupt system controls y loop back mode for internal diagnostic testing 6.10.5.1. uart control registers map r : read only, w : write only, r/w : both read and write, c : only value 0 can be written register offset r/w description reset value uart_rbr 0x00 r receive buffer register (dlab = 0) undefined uart_thr 0x00 w transmit holding register (dlab = 0) undefined uart_ier 0x04 r/w interrupt enable register (dlab = 0) 0x 0000_0000 uart_dll 0x00 r/w divisor latch register (ls) (dlab = 1) 0x0000_0000 uart_dlm 0x04 r/w divisor latch register (ms) (dlab = 1) 0x0000_0000 uart_iir 0x08 r interrupt identification register 0x 8181_8181 uart_fcr 0x08 w fifo control register undefined uart_lcr 0x0c r/w line control register 0x0000_0000 uart_mcr 0x10 r/w modem control register (optional) 0x 0000_0000 uart_lsr 0x14 r line status register 0x6060_6060 uart_msr 0x18 r modem status register (optional) 0x0000_0000 uart_tor 0x1c r/w time out register 0x0000_0000 note: real register address = 0xfff8_0000+ (uart number ? 1) * (0x0100) + offset note: all of these registers are implemented 8-bi t in uart design and it will be repeated 4 times before send to apb bus. for example, when arm cp u read register uartn_brr, arm cpu will get uart0_rbr = {rbr[7:0], rbr[7: 0], rbr[7:0], rbr[7:0]}. uart receive buffer register (uart_rbr) register offset r/w description reset value uart_rbr 0x00 r receive buffer register (dlab = 0) undefined free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 263 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 8-bit received data bits descriptions [7:0] 8-bit received data by reading this register, the uart will return an 8-bit data received from sin pin (lsb first). uart transmit holding register (uart_thr) register offset r/w description reset value uart_thr 0x00 w transmit holding register (dlab = 0) undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 8-bit transmitted data bits descriptions [7:0] 8-bit transmitted data by writing to this register, t he uart will send out an 8-bit data through the sout pin (lsb first). free datasheet http:///
W90N745cd/W90N745cdg - 264 - uart interrupt enable register (uart_ier) register offset r/w description reset value uart_ier 0x04 r/w interrupt enable register (dlab = 0) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ndbgack_en msie rlsie threie rdaie bits descriptions [31:5] reserved - [4] ndbgack_en ice debug mode acknowledge enable 0 = when dbgack is high, the uart receiver time-out clock will be held 1 = no matter what dbgack is high or not, the uart receiver timer-out clock will not be held [3] msie modem status interrupt (irpt_mos) enable 0 = mask off irpt_mos 1 = enable irpt_mos [2] rlsie receive line status interrupt (irpt_rls) enable 0 = mask off irpt_rls 1 = enable irpt_rls [1] threie transmit holding register empty interrupt (irpt_thre) enable 0 = mask off irpt_thre 1 = enable irpt_thre [0] rdaie r eceive d ata a vailable i nterrupt (irpt_rda) e nable and time-out interrupt (irpt_tout) enable 0 = mask off irpt_rda and irpt_tout 1 = enable irpt_rda and irpt_tout free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 265 - revision a2 uart divider latch (low byte) register (uart_dll) register offset r/w description reset value uart_dll 0x00 r/w divisor latch register (ls) (dlab = 1) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 baud rate divider (low byte) bits descriptions [7:0] baud rate divider (low byte) the low byte of the baud rate divider uart divisor latch (high byte) register (uart_dlm) register offset r/w description reset value uart_dlm 0x04 r/w divisor latch register (ms) (dlab = 1) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 baud rate divider (high byte) free datasheet http:///
W90N745cd/W90N745cdg - 266 - bits descriptions [7:0] baud rate divider (high byte) the high byte of the baud rate divider this 16-bit divider {dlm, d ll} is used to determine the baud rate as follows baud rate = crystal clock / {16 * [divisor + 2]} note : this definition is different from 16550 uart interrupt identification register (uart_iir) register offset r/w description reset value uart_iir 0x08 r interrupt identification register 0x 8181_8181 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 fmes rftls dms iid nip bits descriptions [7] fmes fifo mode enable status this bit indicates whether the fifo mode is enabled or not. since the fifo mode is always enabling, this bit always shows the logical 1 when cpu is reading this register. [6:5] rftls rx fifo threshold level status these bits show the current setting of receiver fifo threshold level (rtho). the meaning of rtho is defined in the following fcr description. [4] dms dma mode select the dma function is not implemented in this version. when reading iir, the dms is always returned 0. [3:1] iid interrupt identification the iid together with nip indicates t he current interrupt request from uart [0] nip no interrupt pending there is no pending interrupt. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 267 - revision a2 table 6.10.6 interrupt control functions iir [3:0] priority interrupt type interrupt source interrupt reset control - - - 1 -- none none -- 0110 highest receiver line status (irpt_rls) overrun error, parity error, framing error, or break interrupt reading the lsr 0100 second received data available (irpt_rda) receiver fifo threshold level is reached receiver fifo drops below the threshold level 1100 second receiver fifo time-out (irpt_tout) receiver fifo is non-empty and no activities are occurred in the receiver fifo during the tor defined time duration reading the rbr 0010 third transmitter holing register empty (irpt_thre) transmitter holding register empty reading the iir (if source of interrupt is irpt_thre) or writing into the thr 0000 fourth modem status (irpt_mos) the cts, dsr, or dcd bits are changing state or the ri bit is changing from high to low. reading the msr (optional) note: these definitions of bit 7, bit 6, bit 5, and bit 4 are different from the 16550 uart fifo control register (uart_fcr) register offset r/w description reset value uart_fcr 0x08 w fifo control register undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rfitl reserved dms tfr rfr fme free datasheet http:///
W90N745cd/W90N745cdg - 268 - bits descriptions [7:6] rfitl rx fifo interrupt (irpt_rda) trigger level rfitl [7:6] irpt_rda trigger level (bytes) 00 01 01 04 10 08 11 14 [3] dms dma mode select the dma function is not implemented in this version. [2] tfr tx fifo reset setting this bit will generate an osc cycle reset pulse to reset tx fifo. the tx fifo becomes empty (tx pointer is reset to 0) after such reset. this bit is returned to 0 automatically after the reset pulse is generated. [1] rfr rx fifo reset setting this bit will generate an osc cycle reset pulse to reset rx fifo. the rx fifo becomes empty (rx pointer is re set to 0) after such reset. this bit is returned to 0 automatically after the reset pulse is generated. [0] fme fifo mode enable because uart is always operating in t he fifo mode, writing this bit has no effect while reading always gets logical one. this bit must be 1 when other fcr bits are written to; otherwise, they will not be programmed. uart line control register (uart_lcr) register offset r/w description reset value uart_lcr 0x0c r/w line control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 dlab bcb spe epe pbe nsb wls free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 269 - revision a2 bits descriptions [7] dlab divider latch access bit 0 = it is used to access rbr, thr or ier. 1 = it is used to access divisor latch registers {dll, dlm} [6] bcb break control bit when this bit is set to logic 1, the serial data output (sout) is forced to the spacing state (logic 0). this bit acts only on sout and has no effect on the transmitter logic. [5] spe stick parity enable 0 = disable stick parity 1 = parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). this bit has effect only when bit 3 (parity bit enable) is set. [4] epe even parity enable 0 = odd number of logic 1?s are transmi tted or checked in the data word and parity bits. 1 = even number of logic 1?s are transmi tted or checked in the data word and parity bits. this bit has effect only when bi t 3 (parity bit enable) is set. [3] pbe parity bit enable 0 = parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = parity bit is generated or checked betw een the "last data word bit" and "stop bit" of the serial data. [2] nsb number of ?stop bit? 0= one ? stop bit? is generated in the transmitted data 1= one and a half ? stop bit? is generated in the transmitted data when 5-bit word length is selected; two ? stop bit? is generated when 6-, 7- and 8-bit word length is selected. [1:0] wls word length select wls[1:0] character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits free datasheet http:///
W90N745cd/W90N745cdg - 270 - uart modem control re gister (uart_mcr) register offset r/w description reset value uart_mcr 0x10 r/w modem control register (optional) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved lbme reserve reserve reserved dtr# bits descriptions [31:5] reserved - [4] lbme loop-back mode enable 0 = disable 1 = when the loop-back mode is enabled, the following signals are connected internally sout connected to sin and sout pin fixed at logic 1 dtr# connected to dsr# and dtr# pin fixed at logic 1 [3:1] reserved - [0] dtr complement version of dtr# (data-terminal-ready) signal writing 0x00 to mcr, the dtr# bit are set to logic 1?s; writing 0x0f to mcr, the dtr# bit are reset to logic 0?s. uart line status control register (uart_lsr) register offset r/w description reset value uart_lsr 0x14 r line status register 0x6060_6060 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 271 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 err_rx te thre bii fei pei oei rfdr bits descriptions [31:8] reserved - [7] err_rx rx fifo error 0 = rx fifo works normally 1 = there is at least one parity error (pe), framing error (fe), or break indication (bi) in the fifo. err_rx is cleared when cpu reads the lsr and if there are no subsequent errors in the rx fifo. [6] te transmitter empty 0 = either transmitter holding register ( thr - tx fifo) or transmitter shift register ( tsr ) are not empty. 1 = both thr and tsr are empty. [5] thre transmitter holding register empty 0 = thr is not empty. 1 = thr is empty. thre is set when the last data word of tx fifo is transferred to transmitter shift register (tsr). the cpu resets this bit when the thr (or tx fifo) is loaded. this bit also causes the uart to issue an interrupt (irpt_thre) to the cpu when ier [1]=1. [4] bii break interrupt indicator this bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the cpu reads t he contents of the lsr . [3] fei framing error indicator this bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit fo llowing the last data bit or parity bit is detected as a logic 0), and is reset whenever the cp u reads the contents of the lsr . free datasheet http:///
W90N745cd/W90N745cdg - 272 - continued. bits descriptions [2] pei parity error indicator this bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the cpu reads t he contents of the lsr . [1] oei overrun error indicator an overrun error will occur only after the rx fifo is full and the next character has been completely received in the shift register. the character in the shift register is overwritten, but it is not transferred to the rx fifo. oe is indicated to the cpu as s oon as it happens and is reset whenever the cpu reads the c ontents of the lsr. [0] rfdr rx fifo data ready 0 = rx fifo is empty 1 = rx fifo contains at least 1 received data word. lsr [4:2] (bii, fei, pei) are revealed to the cpu when it s associated character is at the top of the rx fifo. these three error indicators are reset w henever the cpu reads the contents of the lsr. lsr [4:1] (bii, fei, pei, oei) are the error conditions that produce a "receiver line status interrupt" (irpt_rls) when ier [2]=1. reading lsr clears irpt_rls. writing lsr is a null operation (not suggested) uart modem status register (uart_msr) register offset r/w description reset value uart_msr 0x18 r modem status register (optional) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved reserved dsr# reserved reserved reserved ddsr reserved free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 273 - revision a2 bits descriptions [31:6] reserved - [5] dsr# complement version of data set ready (dsr#) input (this bit is selected by ip) [4:2] reserved - [1] ddsr dsr# state change (this bit is selected by ip) this bit is set whenever dsr# input has changed state, and it will be reset if the cpu reads the msr. [0] reserved - whenever any of msr [3:0] is set to logic 1, a m odem status interrupt is generated if ier[3]=1. writing msr is a null operation (not suggested). uart time out register (uart_tor) register offset r/w description reset value uart_tor 0x1c r/w time out register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 toie toic bits descriptions [31:8] reserved - [7] toie time out interrupt enable the feature of receiver time out inte rrupt is enabled when tor [7] = ier[0] = 1. [6:0] toic time out interrupt comparator the time out counter resets and star ts counting (the counting clock = baud rate) whenever the rx fifo receives a new data word. once the content of time out counter (tout_cnt) is equal to that of time out interrupt comparator (toic), a receiver time out interrupt (irpt_tout) is generated if tor [7] = ier [0] = 1. a new incoming data word or rx fifo empty clears irpt_tout. free datasheet http:///
W90N745cd/W90N745cdg - 274 - 6.10.6 high speed uart controller the high speed universal asynchronous receiver/transmitter (hs_uart) performs a serial-to- parallel conversion on data characters received from the peripheral, and a parallel-to-serial conversion on data characters received from the cpu. there are five types of interrupts, they are, transmitter fifo empty interrupt, receiver threshold level reaching interrupt , line status interrupt (overrun error or parity error or framing error or break interrupt ) ,time out interrupt, and modem status interrupt . one 64-byte transmitter fifo (tx_fifo) and one 64-byte (plus 3-bit of erro r data per byte) receiver fifo (rx_fifo) has been built in to reduce the number of in terrupts presented to the cpu. the cpu can completely read the status of the uart at any time during t he operation. the reported status information includes the type and condition of the transfer operations being performed by the uart, as well as any error conditions (parity, overrun, fr aming, or break interrupt) found. the uart includes a programmable baud rate generator that is capable of dividing crystal clock input by divisors to produce the clock that transmitter and receiver needed. the equation is baud out = crystal clock / 16 * [divisor + 2]. the uart includes the following features: y transmitter and receiver are buffered with a 64-byte fifo each to reduce the number of interrupts presented to the cpu. y subset of modem contro l function(selected by ip) y fully programmable serial-interface characteristics: ? 5-, 6-, 7-, or 8-bit character ? even, odd, or no-parity bit generation and detection ? 1-, 1&1/2, or 2-stop bit generation ? baud rate generation y false start bit detection y full-prioritized interrupt system controls y not support loop back mode 6.10.6.1. high speed uart control registers map r : read only, w : write only, r/w : both read and write, c : only value 0 can be written register offset r/w description reset value hsuart_rbr 0x00 r receive buffer register (dlab = 0) undefined hsuart_thr 0x00 w transmit holding register (dlab = 0) undefined hsuart_ier 0x04 r/w interrupt e nable register (dlab = 0) 0x0000_0000 hsuart_dll 0x00 r/w divisor latch register (ls)(dlab = 1) 0x0000_0000 hsuart_dlm 0x04 r/w di visor latch register (ms)(dlab = 1) 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 275 - revision a2 continued. register offset r/w description reset value hsuart_iir 0x08 r interrupt identification register 0x8181_8181 hsuart_fcr 0x08 w fifo c ontrol register undefined hsuart_lcr 0x0c r/w line control register 0x0000_0000 hsuart_mcr 0x10 r/w modem control register (optional) 0x0000_0000 hsuart_lsr 0x14 r line status register 0x6060_6060 hsuart_msr 0x18 r modem status register (optional) 0x0000_0000 hsuart_tor 0x1c r/w time out register 0x0000_0000 note: real register address = 0xfff8_0000+ (uart number ? 1) * (0x0100) + offset note: all of these registers are implemented 8-bi t in uart design and it will be repeated 4 times before send to apb bus. for example, when arm cp u read register uart1_brr, arm cpu will get uart1_rbr = {rbr[7:0], _rbr[7 :0], rbr[7:0], rbr[7:0]}. hsuart receive buffer register (hsuart_rbr) register offset r/w description reset value hsuart_rbr 0x00 r receive buffer register (dlab = 0) undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 8-bit received data bits descriptions [7:0] 8-bit received data by reading this register, the uart will return an 8-bit data received from sin pin (lsb first). free datasheet http:///
W90N745cd/W90N745cdg - 276 - hsuart transmit holding register (hsuart_thr) register offset r/w description reset value hsuart_thr 0x00 w transmit holding register (dlab = 0) undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 8-bit transmitted data bits descriptions [7:0] 8-bit transmitted data by writing to this register, the uart will send out an 8-bit data through the sout pin (lsb first). hsuart interrupt enable register (hsuart_ier) register offset r/w description reset value hsuart_ier 0x04 r/w interrupt enable register (dlab = 0) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ndbgack_en msie rlsie threie rdaie free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 277 - revision a2 bits descriptions [31:5] reserved - [4] ndbgack_en ice debug mode acknowledge enable 0 = when dbgack is high, the uart receiver time-out clock will be held 1 = no matter what dbgack is high or not, the uart receiver timer- out clock will not be held [3] msie modem status interrupt (irpt_mos) enable 0 = mask off irpt_mos 1 = enable irpt_mos [2] rlsie receive line status interrupt (irpt_rls) enable 0 = mask off irpt_rls 1 = enable irpt_rls [1] threie transmit holding register empty interrupt (irpt_thre) enable 0 = mask off irpt_thre 1 = enable irpt_thre [0] rdaie r eceive d ata a vailable i nterrupt (irpt_rda) e nable and time-out interrupt (irpt_tout) enable 0 = mask off irpt_rda and irpt_tout 1 = enable irpt_rda and irpt_tout hsuart divider latch (low byte) register (hsuart_dll) register offset r/w description reset value hsuart_dll 0x00 r/w divisor latch register (ls) (dlab = 1) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 baud rate divider (low byte) free datasheet http:///
W90N745cd/W90N745cdg - 278 - bits descriptions [31:8] reserved - [7:0] baud rate divisor (low byte) the low byte of the baud rate divider hsuart divisor latch (high byte) register (hsuart_dlm) register offset r/w description reset value hsuart_dlm 0x04 r/w divisor latch register (ms) (dlab = 1) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 baud rate divider (high byte) bits descriptions [31:8] reserved [7:0] baud rate divisor (high byte) the high byte of the baud rate divider this 16-bit divider {dlm, d ll} is used to determine the baud rate as follows baud rate = crystal clock / {16 * [divisor + 2]} hsuart interrupt identification register (hsuart_iir) register offset r/w description reset value hsuart_iir 0x08 r interrupt identif ication register 0x8181_8181 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 279 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 fmes rftls dms iid nip bits descriptions [31:8] reserved - [7] fmes fifo mode enable status this bit indicates whether the fifo mode is enabled or not. since the fifo mode is always enable, this bit always shows the logical 1 when cpu is reading this register. [6:5] rftls rx fifo threshold level status these bits show the current setting of receiver fifo threshold level (rtho). the meaning of rtho is defined in the following fcr description. [4] dms dma mode select the dma function is not implemented in this version. when reading iir, the dms is always returned 0. [3:1] iid interrupt identification the iid together with nip indicates the current interrupt request from uart. [0] nip no interrupt pending there is no pending interrupt. free datasheet http:///
W90N745cd/W90N745cdg - 280 - interrupt control functions iir [3:0] priority interrupt type interrupt source interrupt reset control - - - 1 -- none none -- 0110 highest receiver line status (irpt_rls) overrun error, parity error, framing error, or break interrupt reading the lsr 0100 second received data available (irpt_rda) receiver fifo threshold level is reached receiver fifo drops below the threshold level 1100 second receiver fifo time- out (irpt_tout) receiver fifo is non- empty and no activities are occurred in the receiver fifo during the tor defined time duration reading the rbr 0010 third transmitter holing register empty (irpt_thre) transmitter holding register empty reading the iir (if source of interrupt is irpt_thre) or writing into the thr 0000 fourth modem status (irpt_mos) the cts bits are changing state . reading the msr (optional) note : these definitions of bit 7, bit 6, bi t 5, and bit 4 are different from the 16550. hsuart fifo control register (hsuart_fcr) register offset r/w description reset value hsuart_fcr 0x08 w fifo control register undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rfitl dms tfr rfr fme free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 281 - revision a2 bits descriptions [31:8] reserved - [7:4] rfitl rx fifo interrupt (irpt_rda) trigger level rfitl irpt_rda trigger level (bytes) 0000 01 0001 04 0010 08 0011 14 0100 30 0101 46 0110 62 others 62 [3] dms dma mode select the dma function is not implemented in this version. [2] tfr tx fifo reset setting this bit will generate an osc cycle reset pulse to reset tx fifo. the tx fifo becomes empty (tx pointer is reset to 0) after such reset. this bit is returned to 0 automatica lly after the reset pulse is generated. [1] rfr rx fifo reset setting this bit will generate an osc cycle reset pulse to reset rx fifo. the rx fifo becomes empty (rx pointer is reset to 0) after such reset. this bit is returned to 0 automatica lly after the reset pulse is generated. [0] fme fifo mode enable because uart is always operating in the fifo mode, writing this bit has no effect while reading always gets logical one. this bit must be 1 when other fcr bits are written to; ot herwise, they will not be programmed. free datasheet http:///
W90N745cd/W90N745cdg - 282 - hsuart line control register (hsuart_lcr) register offset r/w description reset value hsuart_lcr 0x0c r/w line control register 0x0000_0000 bits descriptions [31:8] reserved - [7] dlab divider latch access bit 0 = it is used to access rbr, thr or ier. 1 = it is used to access divisor latch registers {dll, dlm}. [6] bcb break control bit when this bit is set to logic 1, the serial data output (sout) is forced to the spacing state (logic 0). this bit acts only on sout and has no effect on the transmitter logic. [5] spe stick parity enable 0 = disable stick parity 1 = parity bit is transmitted and checked as a logic 1 if bit 4 is 0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). this bit has effect only when bit 3 (parity bit enable) is set. [4] epe even parity enable 0 = odd number of logic 1?s are transmitted or checked in the data word and parity bits. 1 = even number of logic 1?s are transmitted or checked in the data word and parity bits. this bit has effect only when bi t 3 (parity bit enable) is set. [3] pbe parity bit enable 0 = parity bit is not generated (transmit data) or checked (receive data) during transfer. 1 = parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. [2] nsb number of ?stop bit? 0= one ? stop bit? is generated in the transmitted data 1= one and a half ? stop bit? is generated in the transmitted data when 5-bit word length is selected; two ? stop bit? is generated when 6-, 7- and 8-bit word length is selected. [1:0] wls word length select wls[1:0] character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 283 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 dlab bcb spe epe pbe nsb wls hsuart modem control register (hsuart_mcr) register offset r/w description reset value hsuart_mcr 0x10 r/w modem control register (optional) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved lbme reserved rts reserved bits descriptions [31:5] reserved - [4] lbme loop-back mode enable 0 = disable 1 = when the loop-back mode is enabled, the following signals are connected internally: sout connected to sin and sout pin fixed at logic 1 rts# connected to cts# and rts# pin fixed at logic 1 free datasheet http:///
W90N745cd/W90N745cdg - 284 - continued. bits descriptions [3:2] reserved - [1] rts# complement version of rts# (request-to-send) signal writing 0x00 to mcr, rts# bit are set to logic 1?s; writing 0x0f to mcr, rts# bit are reset to logic 0?s. [0] reserved - hsuart line status control register (hsuart_lsr) register offset r/w description reset value hsuart_lsr 0x14 r line status register 0x6060_6060 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 err_rx te thre bii fei pei oei rfdr bits descriptions [31:8] reserved [7] err_rx rx fifo error 0 = rx fifo works normally 1 = there is at least one parity error (pe), framing error (fe), or break indication (bi) in the fifo. err_ rx is cleared when cpu reads the lsr and if there are no subsequent errors in the rx fifo. [6] te transmitter empty 0 = either transmitter holding register ( thr - tx fifo) or transmitter shift register ( tsr ) are not empty. 1 = both thr and tsr are empty. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 285 - revision a2 continued. bits descriptions [5] thre transmitter holding register empty 0 = thr is not empty. 1 = thr is empty. thre is set when the last data word of tx fifo is transferred to transmitter shift register (tsr). t he cpu resets this bit when the thr (or tx fifo) is loaded. this bit also causes the uart to issue an interrupt (irpt_thre) to the cpu when ier [1]=1. [4] bii break interrupt indicator this bit is set to a logic 1 whenever the received data input is held in the "spacing state" (logic 0) for longer t han a full word transmission time (that is, the total time of "start bit" + dat a bits + parity + stop bits) and is reset whenever the cpu reads t he contents of the lsr . [3] fei framing error indicator this bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit fo llowing the last data bit or parity bit is detected as a logic 0), and is reset whenever the cpu reads the contents of the lsr . [2] pei parity error indicator this bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the cpu reads t he contents of the lsr . [1] oei overrun error indicator an overrun error will occur only after the rx fifo is full and the next character has been completely received in the shift register. the character in the shift register is overwritten, but it is not transferred to the rx fifo. oe is indicated to the cpu as s oon as it happens and is reset whenever the cpu reads the c ontents of the lsr. [0] rfdr rx fifo data ready 0 = rx fifo is empty 1 = rx fifo contains at least 1 received data word. lsr [4:2] (bii, fei, pei) are revealed to the cpu when it s associated character is at the top of the rx fifo. these three error indicators are reset w henever the cpu reads the contents of the lsr. lsr [4:1] (bii, fei, pei, oei) are the error conditions that produce a "receiver line status interrupt" (irpt_rls) when ier [2]=1. reading lsr clears irpt_rls. writing lsr is a null operation (not suggested). free datasheet http:///
W90N745cd/W90N745cdg - 286 - hsuart modem status register (hsuart_msr) register offset r/w description reset value hsuart_msr 0x18 r modem status register (optional) 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved cts# reserved dcts bits descriptions [31:5] reserved - [4] cts# complement version of clear to send (cts#) input (this bit is selected by ip) [3:1] reserved - [0] dcts cts# state change (this bit is selected by ip) this bit is set whenever cts# input has changed state, and it will be reset if the cpu reads the msr. whenever any of msr [0] is set to logic 1, a modem status interrupt is gener ated if ier[3]=1. writing msr is a null operation (not suggested). free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 287 - revision a2 hsuart time out register (hsuart_tor) register offset r/w description reset value hsuart_tor 0x1c r/w time out register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 toie toic bits descriptions [31:8] reserved - [7] toie time out interrupt enable the feature of receiver time out interrupt is enabled only when tor [7] = ier[0] = 1. [6:0] toic time out interrupt comparator the time out counter resets and star ts counting (the counting clock = baud rate) whenever the rx fifo receives a new data word. once the content of time out counter (tout_cnt) is equal to that of time out interrupt comparator (toic), a receiver time out interrupt (irpt_tout) is generated if tor [7] = ier [0] = 1. a new incoming data word or rx fifo empty clears irpt_tout. free datasheet http:///
W90N745cd/W90N745cdg - 288 - 6.11 timer/watchdog controller 6.11.1 general timer controller the timer module includes two channels, timer0 and timer1, which allow you to easily implement a counting scheme for use. the timer can perfo rm functions like frequency measurement, event counting, interval measurement, clock generation, delay timing, and so on. the timer possesses features such as adjustable resolution, programm able counting period, and detailed information. the timer can generate an interrupt signal upon timeout, or provide the current value of count during operation. the general timer controller in cludes the following features y amba apb interface compatible y two channels with a 8-bit presale count er/24-bit down counter and an interrupt request each y independent clock source for each channel y maximum uninterrupted time = (1 / 25 mh z) * (256) * (2^24), if tclk = 25 mhz 6.11.2 watchdog timer 6.11.3 timer control registers map r : read only, w : write only, r/w : both read and write register address r/w/c description reset value tcsr0 0xfff8_1000 r/w timer control and status register 0 0x0000_0005 tcsr1 0xfff8_1004 r/w timer control and status register 1 0x0000_0005 ticr0 0xfff8_1008 r/w timer initial control register 0 0x0000_0000 ticr1 0xfff8_100c r/w timer initial control register 1 0x0000_0000 tdr0 0xfff8_1010 r timer data register 0 0x0000_0000 tdr1 0xfff8_1014 r timer data register 1 0x0000_0000 tisr 0xfff8_1018 r/w timer interrupt status register 0x0000_0000 wtcr 0xfff8_101c r/w watchdog timer control register 0x0000_0400 timer control register 0/1 (tcsr 0/1) register address r/w description reset value tcsr0 0xfff8_1000 r/w timer contro l and status register 0 0x0000_0005 tcsr1 0xfff8_1004 r/w timer contro l and status register 1 0x0000_0005 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 289 - revision a2 31 30 29 28 27 26 25 24 ndbgack_en cen ie mode[1:0] crst cact reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 prescale[7:0] bits descriptions [31] ndbgack_en ice debug mode acknowledge enable 0 = when dbgack is high, t he timer counter will be held 1 = no matter dbgack is high or not, the timer counter will not be held [30] cen counter enable 0 = stops/suspends counting 1 = starts counting [29] ie interrupt enable 0 = disable timer interrupt. 1 = enable timer interrupt. if timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter decrements to zero. [28:27] mode timer operating mode mode timer operating mode 00 the timer is operating in the one-shot mode. the associated interrupt signal is generated once (if ie is enabled) and cen is automatically cleared then. 01 the timer is operating in the periodic mode. the associated interrupt signal is generated periodically (if ie is enabled). 10 the timer is operating in the toggle mode. the interrupt signal is generated periodically (if ie is enabled). and the associated signal (tout) is changing back and forth with 50% duty cycle. 11 reserved. free datasheet http:///
W90N745cd/W90N745cdg - 290 - continued bits descriptions [26] crst counter reset set this bit will reset the timer counter, and also force cen to 0 . 0 = no effect. 1 = reset timer?s prescale counter, internal 24-bit counter and cen. [25] cact timer is in active this bit indicates the counter status of timer. 0 = timer is not active. 1 = timer is in active. [24:8] reserved reserved [7:0] prescale prescale clock input is divided by prescale+1 before it is fed to the counter. if prescale=0, t hen there is no scaling. timer initial count register 0/1 (ticr0/1) register address r/w description reset value ticr0 0xfff8_1008 r/w timer initial control register 0 0x0000_0000 ticr1 0xfff8_100c r/w timer initial control register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 tic [23:16] 15 14 13 12 11 10 9 8 tic [15:8] 7 6 5 4 3 2 1 0 tic [7:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 291 - revision a2 bits descriptions [31:24] reserved reserved [23:0] tic timer initial count this is a 24-bit value representing the initial count. timer will reload this value whenever the count er is decremented to zero. note1: never write 0x0 in tic, or the core will run into unknown state. note2: no matter cen is 0 or 1, whenever software write a new value into this register, timer w ill restart counting using this new value and abort previous count. timer data register 0/1 (tdr0/1) register address r/w description reset value tdr0 0xfff8_10010 r timer data register 0 0x0000_0000 tdr1 0xfff8_10014 r timer data register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 tdr [23:16] 15 14 13 12 11 10 9 8 tdr [15:8] 7 6 5 4 3 2 1 0 tdr [7:0] bits descriptions [31:24] reserved reserved [23:0] tdr timer data register the current count is registered in this 24-bit value. note: software can read a correct current value on this register only when cen = 0 , or the value represents here could not be a correct one. free datasheet http:///
W90N745cd/W90N745cdg - 292 - free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 293 - revision a2 timer interrupt status register (tisr) register address r/w description reset value tisr 0xfff8_1018 r/w timer interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved tif1 tif0 bits descriptions [1] tif1 timer interrupt flag 1 this bit indicates the interrupt status of timer channel 1. 0 = it indicates that the timer 1 dose not countdown to zero yet. 1 = it indicates that the counter of timer 1 has decremented to zero. the interrupt flag is set if it was enable. note : this bit is read only, but can be cleared by writing 1 to this bit. [0] tif0 timer interrupt flag 0 this bit indicates the interrupt status of timer channel 0. 0 = it indicates that the timer 0 dose not countdown to zero yet. 1 = it indicates that the counter of timer 0 has decremented to zero. the interrupt flag is set if it was enable. note : this bit is read only, but can be cleared by writing 1 to this bit. watchdog timer control register (wtcr) register address r/w description reset value wtcr 0xfff8_101c r/w watchdog timer control register 0x0000_0400 free datasheet http:///
W90N745cd/W90N745cdg - 294 - 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved wtclk n dbgack_en wttme 7 6 5 4 3 2 1 0 wte wtie wtis wtif wtrf wtre wtr bits descriptions [31:11] reserved reserved [10] wtclk watchdog timer clock this bit is used for deciding whether the watchdog timer clock input is divided by 256 or not. clock source of watchdog timer is crystal input. 0 = using original clock input 1 = the clock input will be divided by 256 note: when wttme = 1, set this bit has no effect on wdt clock (using original clock input). [9] ndbgack_en ice debug mode acknowledge enable 0 = when dbgack is high, the watchdog timer counter will be held 1 = no matter dbgack is high or not, the watchdog timer counter will not be held [8] wttme watchdog timer test mode enable for reasons of efficiency, the 26-bit counter within the watchdog timer is considered as two independent 13-bit counters in the test mode. they are operated concurrent ly and separately during the test. this approach can save a lot of ti me spent in the test. when the 13- bit counter overflows, a watc hdog timer interrupt is generated. 0 = put the watchdog timer in normal operating mode 1 = put the watchdog timer in test mode [7] wte watchdog timer enable 0 = disable the watchdog timer (this action will reset the internal counter) 1 = enable the watchdog timer free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 295 - revision a2 continued bits descriptions [6] wtie watchdog timer interrupt enable 0 = disable the watchdog timer interrupt 1 = enable the watchdog timer interrupt [5:4] wtis watchdog timer interval select these two bits select the interval for the watchdog timer. no matter which interval is chosen, the reset timeout is always occurred 512 wdt clock cycles later than the interrupt timeout. wtis interrupt timeout reset timeout real time interval (clk=15mhz/256) 00 2 14 clocks 2 14 + 1024 clocks 0.28 sec. 01 2 16 clocks 2 16 + 1024 clocks 1.12 sec. 10 2 18 clocks 2 18 + 1024 clocks 4.47 sec. 11 2 20 clocks 2 20 + 1024 clocks 17.9 sec. [3] wtif watchdog timer interrupt flag if the watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the watchdog timer interrupt has occurred. if the watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. 0 = watchdog timer interrupt does not occur 1 = watchdog timer interrupt occurs note : this bit is read only, but can be cleared by writing 1 to this bit. [2] wtrf watchdog timer reset flag when the watchdog timer initiates a reset, the hardware will set this bit. this flag can be read by software to determine the source of reset. software is responsible to clear it up manually. if wtre is disabled, then the watchdog timer has no effect on this bit. 0 = watchdog timer reset does not occur 1 = watchdog timer reset occurs note : this bit is read only, but can be cleared by writing 1 to this bit. free datasheet http:///
W90N745cd/W90N745cdg - 296 - continued bits descriptions [1] wtre watchdog timer reset enable setting this bit will enable the watchdog timer reset function. 0 = disable watchdog timer reset function 1 = enable watchdog timer reset function [0] wtr watchdog timer reset this bit brings the watchdog timer in to a known state. it helps reset the watchdog timer before a timeout si tuation occurring. failing to set wtr before timeout will initiates an interrupt if wtie is set. if the wtre bit is set, watchdog timer reset will be occurred 512 wdt clock cycles after timeout. this bit is self-clearing. 0 = no operation 1 = reset the contents of the watchdog timer free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 297 - revision a2 6.12 advanced interrupt controller an interrupt temporarily changes the sequence of program execution to react to a particular event such as power failure, watchdog timer timeou t, transmit/receive reques t from ethernet mac controller, and so on. the arm7tdmi proce ssor provides two modes of interrupt, the fast interrupt (fiq) mode for critical session and the interrupt (irq) mode for general purpose. the irq exception is occurred when the nirq input is asserted. simila rly, the fiq exception is occurred when the nfiq input is asserted. the fiq has privilege over t he irq and can preempt an ongoing irq. it is possible to ignore the fiq and the irq by setting the f and i bits in the current program status register (cpsr) . the W90N745 incorporates the advanced interrupt controller (aic) that is capable of dealing with the interrupt requests from a total of 32 different sources. currently, 31 interrupt sources are defined. each interrupt source is uniquely assigned to an interrupt channel . for example, the watchdog timer interrupt is assigned to channel 1. the aic implement s a proprietary eight-level priority scheme that differentiates the available 31 interrupt sources into eight priority levels. interrupt sources within the priority level 0 have the highest priority and the prio rity level 7 has the lowest. to work this scheme properly, you must specify a certain priority level to each interrupt source during power-on initialization; otherwise, the syst em shall behave unexpectedly. within each priority level, interrupt source that is positioned in a lower channel has a hi gher priority. interrupt s ource that is active, enabled, and positioned in the lowest channel within t he priority level 0 is promoted to the fiq. interrupt sources within the priority levels ot her than 0 can petition for the irq. the irq can be preempted by the occurrence of the fiq. interrupt nesting is performed automatically by the aic. though interrupt sources originated from the W90N745 it self are intrinsically high-level sensitive, the aic can be configured as either low-level sensitiv e, high-level sensitive, negative-edge triggered, or positive-edge triggered to each interrupt source. w hen the W90N745 is put in the test mode, all interrupt sources must be confi gured as positive-edge triggered. the advanced interrupt controller includes the following features: y amba apb bus interface y external interrupts can be programmed as either edge-triggered or level-sensitive y external interrupts can be programmed as either low-active or high-active y has flags to reflect the status of each interrupt source y individual mask for each interrupt source y proprietary 8-level interrupt scheme to ease the burden from the interrupt y priority methodology is adopted to allow for interrupt daisy-chaining y automatically masking out the lower priority interrupt during interrupt nesting y automatically clearing the interrupt flag when the external interrupt source is programmed to be edge-triggered free datasheet http:///
W90N745cd/W90N745cdg - 298 - 6.12.1 interrupt sources table 6.12.1 W90N745 interrupt sources priority name mode source 1 (highest) wdt_int positive level watch dog timer interrupt 2 nirq0 programmable external interrupt 0 3 nirq1 programmable external interrupt 1 4 reserved - - 5 reserved - - 6 ac97_int positive level ac97 interrupt 7 reserved - - 8 reserved - - 9 uart_int0 positive level uart interrupt0 10 uart_int1 positive level uart interrupt1 11 uart_int2 positive level uart interrupt2 12 uart_int3 positive level uart interrupt3 13 t_int0 positive level timer interrupt 0 14 t_int1 positive level timer interrupt 1 15 usbh_int0 positive level usb host interrupt 0 16 usbh_int1 positive level usb host interrupt 1 17 emctx_int positive level emc tx interrupt 18 emcrx_int positive level emc rx interrupt 19 gdma_int0 positive level gdma channel interrupt 0 20 gdma_int1 positive level gdma channel interrupt 1 21 reserved - - 22 usbd_int positive level usb device interrupt 23 reserved - - 24 reserved - - 25 i 2 c_int0 positive level i 2 c interrupt0 26 i 2 c_int1 positive level i 2 c interrupt1 27 ssp_int positive level ssp interrupt 28 pwm _int positive level pwm timer interrupt 29 kpi_int positive level keypad interrupt 30 ps2_int positive level ps2 interrupt 31 nirq2/3_int positive level gpio0 & gpio30 interrupt free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 299 - revision a2 aic functional description hardware interrupt vectoring the hardware interrupt vectoring can be used to shor ten the interrupt latency. if not used, priority determination must be carried out by software. w hen the interrupt priority encoding register (aic_iper) is read, it will return an integer repr esenting the channel that is active and having the highest priority. this integer is equivalent to multipli ed by 4 (shifted left two bits to word-align it) such that it may be used directly to index into a branc h table to select the appropriate interrupt service routine vector. priority controller an 8-level priority encoder controls the nirq line. each interrupt source belongs to priority group between of 0 to 7. group 0 has the highest prio rity and group 7 the lowest. when more than one unmasked interrupt channels are active at a time, the in terrupt with the highest priority is serviced first. if all active interrupts have equal priority, the interr upt with the lowest interrupt source number is serviced first. the current priority level is defined as the priority le vel of the interrupt with the highest priority at the time the register aic_iper is read. in the case when a higher priority unmasked interrupt occurs while an interrupt already exits, there are two possi ble outcomes depending on whether the aic_iper has been read. if the processor has already read the aic_iper and caused the nirq line to be de-asserted, then the nirq line is reasserted. when the processor has enabled nested interrupts and reads the aic_iper again, it reads the new, higher priority interrupt vector . at the same time, the current priority level is updated to the higher priority. if the aic_iper has not been read after the nirq line has been asserted, then the processor will read the new higher priority interrupt vector in the ai c_iper register and the current priority level is updated. when the end of service command regi ster (aic_eoscr) is written, the current interrupt level is updated with the last stored interrupt level from the stack (if any). therefore, at the end of a higher priority interrupt, the aic returns to the previous state corresponding to the preceding lower priority interrupt which had been interrupted. interrupt handling when the irq line is asserted, the interrupt handler must read the aic_iper as soon as possible. this can de-assert the nirq request to the processo r and clears the interrupt if it is programmed to be edge triggered. this allows the aic to assert t he nirq line again when a higher priority unmasked interrupt occurs. the aic_eoscr (end of service command register) must be writt en at the end of the interrupt service routine. this permits pending interrupts to be serviced. free datasheet http:///
W90N745cd/W90N745cdg - 300 - interrupt masking each interrupt source, including fiq, can be enabl ed or disabled individually by using the command registers aic_mecr and aic_mdcr. the status of interrupt mask can be read in the read only register aic_imr. a disabled interrupt doesn?t affect the servicing of other interrupts. interrupt clearing and setting all interrupt sources (including fiq) can be individua lly set or clear by respectively writing to the registers aic_sscr and aic_sccr w hen they are programmed to be edge triggered. this feature of the aic is useful in auto-testing or software debugging. fake interrupt when the aic asserts the nirq li ne, the processor enters interr upt mode and the interrupt handler reads the aic_iper, it may happen that aic de-assert s the nirq line after the processor has taken into account the nirq assertion and before the read of the aic_iper. this behavior is called a fake interrupt. the aic is able to detect these fake interrupts and re turns all zero when aic_iper is read. the same mechanism of fake interrupt occurs if the processo r reads the aic_iper (app lication software or ice) when there is no interrupt pending. the current priority level is not updated in this situation. hence, the aic_eoscr shouldn?t be written. ice/debug mode this mode allows reading of the aic_iper without performing the associated automatic operations. this is necessary when working with a debug sy stem. when an ice or debug monitor reads the aic user interface, the aic_iper can be read. th is has the following consequences in normal mode: y if there is no enabled pending interrupt, the fake vector will be returned. y if an enabled interrupt with a higher priori ty than the current one is pending, it will be stacked. in the second case, an end-of-service command would be necessary to restore the state of the aic. this operation is generally not performed by t he debug system. therefore, the debug system would become strongly intrusive, and could cause the application to enter an undesired state. this can be avoided by using ice/debug mode. when this mode is enabled. the aic performs interrupt stacking only when a write access is per formed on the aic_iper. hence, the interrupt service routine must write to the ai c_iper (any value) just after r eading it. when aic_iper is written, the new status of aic, including the value of inte rrupt source number regist er (aic_isnr), is updated with the value that is kept at previous reading of aic_iper the debug system must not write to the aic_iper as this would cause undesirable effects. the following table shows the main steps of an in terrupt and the order in which they are performed according to the mode: free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 301 - revision a2 action normal mode ice/debug mode calculate active interrupt read aic_iper read aic_iper determine and return the vector of the ac tive interrupt read aic_iper read aic_iper push on internal stack the current priori ty level read aic_iper write aic_iper acknowledge the interrupt (note 1) read aic_iper write aic_iper no effect (note 2) read aic_iper notes: y nirq de-assertion and automatic interrupt clearing if the source is programmed as level sensitive. y note that software which has been wr itten and debugged using this mode will run correctly in normal mode without modificati on. however, in normal mode writing to aic_iper has no effect and can be removed to optimize the code 6.12.2 aic registers map register address r/w description reset value aic_scr1 0xfff8_2004 r/w source control register 1 0x0000_0047 aic_scr2 0xfff8_2008 r/w source control register 2 0x0000_0047 aic_scr3 0xfff8_200c r/w source control register 3 0x0000_0047 aic_scr4 0xfff8_2010 r/w source control register 4 0x0000_0047 aic_scr5 0xfff8_2014 r/w source control register 5 0x0000_0047 aic_scr6 0xfff8_2018 r/w source control register 6 0x0000_0047 aic_scr7 0xfff8_201c r/w source control register 7 0x0000_0047 aic_scr8 0xfff8_2020 r/w source control register 8 0x0000_0047 aic_scr9 0xfff8_2024 r/w source control register 9 0x0000_0047 aic_scr10 0xfff8_2028 r/w source control register 10 0x0000_0047 aic_scr11 0xfff8_202c r/w source control register 11 0x0000_0047 aic_scr12 0xfff8_2030 r/w source control register 12 0x0000_0047 aic_scr13 0xfff8_2034 r/w source control register 13 0x0000_0047 aic_scr14 0xfff8_2038 r/w source control register 14 0x0000_0047 aic_scr15 0xfff8_203c r/w source control register 15 0x0000_0047 free datasheet http:///
W90N745cd/W90N745cdg - 302 - aic registers map, continued register address r/w description reset value aic_scr16 0xfff8_2040 r/w source control register 16 0x0000_0047 aic_scr17 0xfff8_2044 r/w source control register 17 0x0000_0047 aic_scr18 0xfff8_2048 r/w source control register 18 0x0000_0047 aic_scr19 0xfff8_204c r/w source control register 19 0x0000_0047 aic_scr20 0xfff8_2050 r/w source control register 20 0x0000_0047 aic_scr21 0xfff8_2054 r/w source control register 21 0x0000_0047 aic_scr22 0xfff8_2058 r/w source control register 22 0x0000_0047 aic_scr23 0xfff8_205c r/w source control register 23 0x0000_0047 aic_scr24 0xfff8_2060 r/w source control register 24 0x0000_0047 aic_scr25 0xfff8_2064 r/w source control register 25 0x0000_0047 aic_scr26 0xfff8_2068 r/w source control register 26 0x0000_0047 aic_scr27 0xfff8_206c r/w source control register 27 0x0000_0047 aic_scr28 0xfff8_2070 r/w source control register 28 0x0000_0047 aic_scr29 0xfff8_2074 r/w source control register 29 0x0000_0047 aic_scr30 0xfff8_2078 r/w source control register 30 0x0000_0047 aic_scr31 0xfff8_207c r/w source control register 31 0x0000_0047 aic_irsr 0xfff8_2100 r interrupt raw status register 0x0000_0000 aic_iasr 0xfff8_2104 r interrupt active status register 0x0000_0000 aic_isr 0xfff8_2108 r interrupt status register 0x0000_0000 aic_iper 0xfff8_210c r interrupt priority encoding register 0x0000_0000 aic_isnr 0xfff8_2110 r interrupt source number register 0x0000_0000 aic_imr 0xfff8_2114 r interrupt mask register 0x0000_0000 aic_oisr 0xfff8_2118 r output interrupt status register 0x0000_0000 aic_mecr 0xfff8_2120 w mask enable command register u ndefined aic_mdcr 0xfff8_2124 w mask disable command register u ndefined aic_sscr 0xfff8_2128 w source set command register u ndefined aic_sccr 0xfff8_212c w source clear command register u ndefined aic_eoscr 0xfff8_2130 w end of service command register u ndefined aic_test 0xfff8_2200 w ice/debug mode register u ndefined free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 303 - revision a2 aic source control registers (aic_scr1 ~ aic_scr31) register address r/w description reset value aic_scr1 0xfff8_2004 r/w source control register 1 0x0000_0047 aic_scr2 0xfff8_2008 r/w source control register 2 0x0000_0047 y y y y y y y y y y y y y y y aic_scr28 0xfff8_2070 r/w source control register 28 0x0000_0047 aic_scr29 0xfff8_2074 r/w source control register 29 0x0000_0047 aic_scr30 0xfff8_2078 r/w source control register 30 0x0000_0047 aic_scr31 0xfff8_207c r/w source control register 31 0x0000_0047 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 srctype reserved priority bits descriptions [31:8] reserved reserved [7:6] srctype interrupt source type whether an interrupt source is consi dered active or not by the aic is subject to the settings of this field. interrupt sources other than nirq0, nirq1 should be configured as leve l sensitive during normal operation unless in the testing situation. srctype [7:6] interrupt source type 0 0 low-level sensitive 0 1 high-level sensitive 1 0 negative-edge triggered 1 1 positive-edge triggered free datasheet http:///
W90N745cd/W90N745cdg - 304 - continued bits descriptions [5:3] reserved reserved [2:0] priority priority level every interrupt source must be assigned a priority level during initiation. among them, priority level 0 has the highest priority and priority level 7 the lowest. interrupt sources with priority level 0 are promoted to fiq. interrupt sources with priority level other than 0 belong to irq. for interrupt sources of the same priority level that located in the lower channel number has higher priority. aic interrupt raw status register (aic_irsr) register address r/w description reset value aic_irsr 0xfff8_2100 r interrupt raw status register 0x0000_0000 31 30 29 28 27 26 25 24 irs31 irs30 irs29 irs28 irs27 irs26 irs25 irs24 23 22 21 20 19 18 17 16 irs23 irs22 irs21 irs20 irs19 irs18 irs17 irs16 15 14 13 12 11 10 9 8 irs15 irs14 irs13 irs12 irs11 irs10 irs9 irs8 7 6 5 4 3 2 1 0 irs7 irs6 irs5 irs4 irs3 irs2 irs1 reserve d bits descriptions [31:1] irsx this register records the intrinsic state within each interrupt channel. irs x : interrupt status indicate the intrinsic status of the corresponding interrupt source 0 = interrupt channel is in the voltage level 0 1 = interrupt channel is in the voltage level 1 [0] reserved reserved free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 305 - revision a2 aic interrupt active status register (aic_iasr) register address r/w description reset value aic_iasr 0xfff8_2104 r interrupt active status register 0x0000_0000 31 30 29 28 27 26 25 24 ias31 ias30 ias29 ias28 ias27 ias26 ias25 ias24 23 22 21 20 19 18 17 16 ias23 ias22 ias21 ias20 ias19 ias18 ias17 ias16 15 14 13 12 11 10 9 8 ias15 ias14 ias13 ias12 ias11 ias10 ias9 ias8 7 6 5 4 3 2 1 0 ias7 ias6 ias5 ias4 ias3 ias2 ias1 reserve d bits descriptions [31:1] iasx this register indicates the stat us of each interrupt channel in consideration of the interrupt source type as defined in the corresponding source control regist er, but regardless of its mask setting. ias x : interrupt active status indicate the status of the corresponding interrupt source 0 = corresponding interrupt channel is inactive 1 = corresponding interrupt channel is active [0] reserved reserved aic interrupt status register (aic_isr) register address r/w description reset value aic_isr 0xfff8_2108 r interrupt status register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 306 - 31 30 29 28 27 26 25 24 is31 is30 is29 is28 is27 is26 is25 is24 23 22 21 20 19 18 17 16 is23 is22 is21 is20 is19 is18 is17 is16 15 14 13 12 11 10 9 8 is15 is14 is13 is12 is11 is10 is9 is8 7 6 5 4 3 2 1 0 is7 is6 is5 is4 is3 is2 is1 reserve d bits descriptions [31:1] isx this register identifies those inte rrupt channels whose are both active and enabled. is x : interrupt status indicates the status of corresponding interrupt channel 0 = two possibilities: (1) the corresponding interrupt channel is inactive no matter whether it is enabled or disabled; (2) it is active but not enabled 1 = corresponding interrupt channel is both active and enabled (can assert an interrupt) [0] reserved reserved aic irq priority encoding register (aic_iper) register address r/w description reset value aic_iper 0xfff8_210c r interrupt priority encoding register 0x0000_0000 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 vector 0 0 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 307 - revision a2 bits descriptions [6:2] vector when the aic generates the interrupt, vector represents the interrupt channel number that is active, enabled, and has the highest priority. if the representing interrupt channel possesses a priority level 0, then the interrupt asserted is fiq; otherwise, it is irq. the value of vector is copied to the register aic_isnr thereafter by the aic. this register was restored a value 0 after it was read by the interrupt handler. this register can help indexing into a branch table to quickly jump to the corresponding interrupt service routine. vector [6:2]: interrupt vector 0 = no interrupt occurs 1 ~ 31 = representing the interrupt channel that is active, enabled, and having the highest priority [0] reserved reserved aic interrupt source number register (aic_isnr) register address r/w description reset value aic_isnr 0xfff8_2110 r interrupt source number register 0x0000_0000 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 irqid bits descriptions [31:5] reserved reserved [4:0] irqid the purpose of this register is to record the interrupt channel number that is active, enabled, and has the highest priority. irqid [4:0]: irq identification stands for the interrupt channel number free datasheet http:///
W90N745cd/W90N745cdg - 308 - aic interrupt mask register (aic_imr) register address r/w description reset value aic_imr 0xfff8_2114 r interrupt mask register 0x0000_0000 31 30 29 28 27 26 25 24 im31 im30 im29 im28 im27 im26 im25 im24 23 22 21 20 19 18 17 16 im23 im22 im21 im20 im19 im18 im17 im16 15 14 13 12 11 10 9 8 im15 im14 im13 im12 im11 im10 im9 im8 7 6 5 4 3 2 1 0 im7 im6 im5 im4 im3 im2 im1 reserve d bits descriptions [31:1] im x im x : interrupt mask this bit determines whether the corresponding interrupt channel is enabled or disabled. every interrupt channel can be active no matter whether it is enabled or disabled. if an interrupt channel is enabled, it does not definitely mean it is acti ve. every interrupt channel can be authorized by the aic only when it is both active and enabled. 0 = corresponding interrupt channel is disabled 1 = corresponding interrupt channel is enabled [0] reserved reserved aic output interrupt status register (aic_oisr) register address r/w description reset value aic_oisr 0xfff8_2118 r output interrupt status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved irq fiq free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 309 - revision a2 the aic classifies the interrupt into fiq and irq. this register indicates whether the asserted interrupt is fiq or irq. if both irq and fiq are equal to 0, it means there is no interrupt occurred. bits descriptions [31:2] reserved reserved [1] irq irq [1]: interrupt request 0 = nirq line is inactive. 1 = nirq line is active. [0] fiq fiq [0]: fast interrupt request 0 = nfiq line is inactive. 1 = nfiq line is active aic mask enable command register (aic_mecr) register address r/w description reset value aic_mecr 0xfff8_2120 w mask enable command register u ndefined 31 30 29 28 27 26 25 24 mec31 mec30 mec29 mec28 mec27 mec26 mec25 mec24 23 22 21 20 19 18 17 16 mec23 mec22 mec21 mec20 mec19 mec18 mec17 mec16 15 14 13 12 11 10 9 8 mec15 mec14 mec13 mec12 mec11 mec10 mec9 mec8 7 6 5 4 3 2 1 0 mec7 mec6 mec5 mec4 mec3 mec2 mec1 reserve d bits descriptions [31:1] mec x mec x: mask enable command 0 = no effect 1 = enables the corresponding interrupt channel [0] reserved reserved free datasheet http:///
W90N745cd/W90N745cdg - 310 - aic mask disable command register (aic_mdcr) register address r/w description reset value aic_mdcr 0xfff8_2124 w mask disable command register u ndefined 31 30 29 28 27 26 25 24 mdc31 mdc30 mdc29 mdc28 mdc27 mdc26 mdc25 mdc24 23 22 21 20 19 18 17 16 mdc23 mdc22 mdc21 mdc20 mdc19 mdc18 mdc17 mdc16 15 14 13 12 11 10 9 8 mdc15 mdc14 mdc13 mdc12 mdc11 mdc10 mdc9 mdc8 7 6 5 4 3 2 1 0 mdc7 mdc6 mdc5 mdc4 mdc3 mdc2 mdc1 reserve d bits descriptions [31:1] mdcx mdc x : mask disable command 0 = no effect 1 = disables the corresponding interrupt channel [0] reserved reserved aic source set command register (aic_sscr) register address r/w description reset value aic_sscr 0xfff8_2128 w source set command register u ndefined 31 30 29 28 27 26 25 24 ssc31 ssc30 ssc29 ssc28 ssc27 ssc26 ssc25 ssc24 23 22 21 20 19 18 17 16 ssc23 ssc22 ssc21 ssc20 ssc19 ssc18 ssc17 ssc16 15 14 13 12 11 10 9 8 ssc15 ssc14 ssc13 ssc12 ssc11 ssc10 ssc9 ssc8 7 6 5 4 3 2 1 0 ssc7 ssc6 ssc5 ssc4 ssc3 ssc2 ssc1 reserve d free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 311 - revision a2 bits descriptions [31:1] sscx when the W90N745 is under debugging or verification , software can activate any interrupt channel by setting the corresponding bit in this register. this feature is us eful in hardware verification or software debugging. sscx: source set command 0 = no effect. 1 = activates the corresponding interrupt channel [0] reserved reserved aic source clear command register (aic_sccr) register address r/w description reset value aic_sccr 0xfff8_212c w source clear command register u ndefined 31 30 29 28 27 26 25 24 scc31 scc30 scc29 scc28 scc27 scc26 scc25 scc24 23 22 21 20 19 18 17 16 scc23 scc22 scc21 scc20 scc19 scc18 scc17 scc16 15 14 13 12 11 10 9 8 scc15 scc14 scc13 scc12 scc11 scc10 scc9 scc8 7 6 5 4 3 2 1 0 scc7 scc6 scc5 scc4 scc3 scc2 scc1 reserve d bits descriptions [31:1] sccx when the W90N745 is under debugging or verification , software can deactivate any interrupt channel by setting the corresponding bit in this register. this feature is us eful in hardware verification or software debugging. scc x : source clear command 0 = no effect. 1 = deactivates the corresponding interrupt channels [0] reserved reserved free datasheet http:///
W90N745cd/W90N745cdg - 312 - aic end of service command register (aic_eoscr) register address r/w description reset value aic_eoscr 0xfff8_2130 w end of service command register u ndefined 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 --- --- --- --- --- --- --- --- 15 14 13 12 11 10 9 8 --- --- --- --- --- --- --- --- 7 6 5 4 3 2 1 0 --- --- --- --- --- --- --- --- bits descriptions [31:0] eoscr this register is used by the interrupt se rvice routine to indicate that it is completely served. thus, the interr upt handler can write any value to this register to indicate the end of its interrupt service. aic ice/debug register (aic_test) register address r/w description reset value aic_test 0xfff8_2200 w ice/debug mode register undefined 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved test free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 313 - revision a2 bits descriptions [31:1] reserved reserved [0] test this register indicates whether aic_iper will be cleared or not after been read. if bit0 of aic_test has been set, ice or debug monitor can read aic_iper for verification and the aic_iper will not be cleared automatically. write access to the ai c_iper will perform the interrupt stacking in this mode. test: ice/debug mode 0 = normal mode. 1 = ice/debug mode. free datasheet http:///
W90N745cd/W90N745cdg - 314 - 6.13 general-purpose input/output the general-purpose input/output ( gpio ) module possesses 31 pins and serves multiple function purposes. each port can be configured by software to meet various system configurations and design requirements. software must configure each pin before starting the main program. if a pin is not used for multiplexed functions, the pin can be configured as i/o port two extended interrupts nirq2 (gpio0 pin) and nirq3 (nwait pin) are used the same interrupt request (channel #31) of aic. it can be programmed as low/ high sensitive or posit ive/negative edge triggered. when interrupt #31 assert in aic, software can poll xistatus status register to identify which interrupt occur. these 31 io pins are divided into 7 groups acco rding to its peripheral interface definition. y port0: 5-pin input/output port y port1: 2-pin input/output port y port2: 10-pin input/output port y port3: reserved y port4: 1-pin input/output port y port5: 13-pin input/output port need updated y port6: reserved table 6.13.1 gpio multiplexed functions table port0 configurable pin functions 0 gpio0 ac97_nreset (i2s_mclk) nirq2 usbpwren 1 gpio1 ac97_datai (i2s_datai) pwm0 dtr3 2 gpio2 ac97_datao (i2s_datao) pwm1 dsr3 3 gpio3 ac97_sync (i2s_lrclk) pwm2 txd3 4 gpio4 ac97_bitclk (i2s_bitclk) pwm3 rxd3 port1 configuration pin functions 0 gpio18 - nxdack - 1 gpio19 - nxdreq - port2 configuration pin functions 0 gpio20 phy_rxerr kpcol0 - 1 gpio21 phy_crsdv kpcol1 - 2 gpio22 phy_rxd[0] kpcol2 - 3 gpio23 phy_rxd[1] kpcol3 - free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 315 - revision a2 table 6.13.1 gpio multiplex ed functions table, continued 4 gpio24 phy_refclk kpcol4 - 5 gpio25 phy_txen kpcol5 - 6 gpio26 phy_txd[0] kpcol6 - 7 gpio27 phy_txd[1] kpcol7 - 8 gpio28 phy_mdio kprow0 - 9 gpio29 phy_mdc kprow1 - port3 configuration pin functions reserved port4 configuration pin functions 0 gpio30 nwait nirq3 - port5 configuration pin functions 0 gpio5 txd0 - - 1 gpio6 rxd0 - - 2 gpio7 txd1 - - 3 gpio8 rxd1 - - 4 gpio9 txd2 cts1 ps2clk 5 gpio10 rxd2 rts1 ps2data 6 gpio11 scl0 sfrm timer0 7 gpio12 sda0 ssptxd timer1 8 gpio13 scl1 sclk kprow3 9 gpio14 sda1 ssprxd kprow2 10 gpio15 nwdog usbpwren - 11 gpio16 nirq0 - - 12 gp1o17 nirq1 usbovrcur - port6 configuration pin function reserved free datasheet http:///
W90N745cd/W90N745cdg - 316 - 6.13.1 gpio register description register address r/w description reset value gpio_cfg0 0xfff8_3000 r/w gpio port0 configuration register 0x0000_0000 gpio_dir0 0xfff8_3004 r/w gpio port0 direction control register 0x0000_0000 gpio_dataout0 0xfff8_3008 r/w gpio port0 data output register 0x0000_0000 gpio_datain0 0xfff8_300c r gpio port0 data input register 0xxxxx_xxxx gpio_cfg1 0xfff8_3010 r/w gpio port1 configuration register 0x0000_0000 gpio_dir1 0xfff8_3014 r/w gpio port1 direction control register 0x0000_0000 gpio_dataout1 0xfff8_3018 r/w gpio port1 data output register 0x0000_0000 gpio_datain1 0xfff8_301c r gpio port1 data input register 0xxxxx_xxxx gpio_cfg2 0xfff8_3020 r/w gpio port2 configuration register 0x0000_0000 gpio_dir2 0xfff8_3024 r/w gpio port2 direction control register 0x0000_0000 gpio_dataout2 0xfff8_3028 r/w gpio port2 data output register 0x0000_0000 gpio_datain2 0xfff8_302c r gpio port2 data input register 0xxxxx_xxxx gpio_cfg4 0xfff8_3040 r/w gpio port4 configuration register 0x0015_5555 gpio_dir4 0xfff8_3044 r/w gpio port4 direction control register 0x0000_0000 gpio_dataout4 0xfff8_3048 r/w gpio port4 data output register 0x0000_0000 gpio_datain4 0xfff8_304c r gpio port4 data input register 0xxxxx_xxxx gpio_cfg5 0xfff8_3050 r/w gpio port5 configuration register 0x0000_0000 gpio_dir5 0xfff8_3054 r/w gpio port5 direction control register 0x0000_0000 gpio_dataout5 0xfff8_3058 r/w gpio port5 data output register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 317 - revision a2 gpio register description, continued. register address r/w description reset value gpio_datain5 0xfff8_305c r gpio port5 data input register 0xxxxx_xxxx gpio_dbncecon 0xfff8_3070 r/w gpio input debounce control register 0x0000_0000 gpio_xicfg 0xfff8_3074 r/w extend interrupt configure register 0xxxxx_xxx0 gpio_xistatus 0xfff8_3078 r/w e xtend interrupt status register 0xxxxx_xxx0 6.13.2 gpio register description gpio port0 configuration register (gpio_cfg0) register address r/w description reset value gpio_cfg0 0xfff8_3000 r/w gpio port0 configuration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved pt0cfg4 7 6 5 4 3 2 1 0 pt0cfg3 pt0cfg2 pt0cfg1 pt0cfg0 11 10 01 00 pt0cfg0 name type name type name type name type port0_0 usb_pwren o nirq2 i ac97reset or i2smclk o gpio0 i/o 11 10 01 00 pt0cfg1 name type name type name type name type port0_1 dtr3 o pwm0 o ac97datai or i2sdatai o gpio1 i/o free datasheet http:///
W90N745cd/W90N745cdg - 318 - continued 11 10 01 00 pt0cfg2 name type name type name type name type port0_2 dsr3 i pwm1 o ac97datao or i2sdatao o gpio2 i/o 11 10 01 00 pt0cfg3 name type name type name type name type port0_3 txd3 o pwm2 o ac97sync or i2slrclk o gpio3 i/o 11 10 01 00 pt0cfg4 name type name type name type name type port0_4 rxd3 o pwm3 o ac97bitclk or i2sbitclk i o gpio4 i/o gpio port0 direction register (gpio_dir0) register address r/w description reset value gpio_dir0 0xfff8_3004 r/w gpio port0 in/out direction control and pull-up enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pupen0[3:0] 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved omden0[4:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 319 - revision a2 bits description [31:20] reserved - [19:16] pupen0 gpio3 -gpio0 port pin internal pull-up resister enable there are 4 bits for this register, the corresponding bit is set to ?1? will enable pull-up resister on io pin. 1 = enable 0 = disable after power on the pull-up resisters are disabled. note: gpio4 is used as ac97 bitclk input, an io pad with schmitt trigger input buffer pdb 04sdgz is implemented for this pin. due to tsmc io library wi thout pull-up register, an external pull-up resister is necessary. [15:5] reserved [4:0] omden0 gpio4 ~gpio0 output mode enable 1 = output mode 0 = input mode note: output mode enable bits are valid only when bit pt0cfg4-0 is configured as general purpose i/o mode. each port pin can be enabled individually by setting the corresponding control bit. gpio port0 data output register (gpio_dataout0) register address r/w description reset value gpio_dataout0 0xfff8_3008 r/w gpio port0 data output register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved dataout0 bits description [31:5] reserved - [4:0] dataout0 port0 data output value writing data to this register will reflect the data value on the corresponding port0 pin when it is configured as general purpose output pin. and writing data to re served bits is not effective. free datasheet http:///
W90N745cd/W90N745cdg - 320 - gpio port0 data input register (gpio_datain0) register address r/w description reset value gpio_datain0 0xfff8_300c r/w gpio port0 data input register 0xxxxx_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved datain0 bits description [31:5] reserved - [4:0] datain0 port0 data input value the datain0 indicates the status of each gpio0~gpio4 port pin regardless of its operation mode. the reserved bits will be read as ?0?. gpio port1 configuration register (gpio_cfg1) register address r/w description reset value gpio_cfg1 0xfff8_3010 r/w gpio port1 configuration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved pt1cfg1 pt1cfg0 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 321 - revision a2 *in the following pin definition, mark with shading is default function. 11 10 01 00 pt1cfg0 name type name type name type name type port1_0 - - - nxdack o gpio18 i/o 11 10 01 00 pt1cfg1 name type name type name type name type port1_1 - - - nxdreq i gpio19 i/o gpio port1 direction register (gpio_dir1) register address r/w description reset value gpio_dir1 0xfff8_3014 r/w gpio port0 in/out direction control and pull-up enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pupen1[1:0] 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved omden1[1:0] bits description [31:18] reserved - [17:16] pupen1 gpio19 ~ gpio18 port pins internal pull-up resister enable this is a 2-bit registers, set corresponding bit to ?1? will enable pull up resister in io pin. 1 = enable 0 = disable after power on the resisters are disabled. [15:2] reserved - free datasheet http:///
W90N745cd/W90N745cdg - 322 - continued. [1:0] omden1 gpio19 ~ gpio18 output mode enable 1 = enable 0 = disable note: output mode enable bits are valid only when bit pt1cfg1-0 is configured as general purpose i/o mode. each port pin can be enabled individually by setting the corresponding control bit. gpio port1 data output register (gpio_dataout1) register address r/w description reset value gpio_dataout1 0xfff8_3018 r/w gpio port1 data output register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved dataout1[1:0] bits description [31:2] reserved - [1:0] dataout1 port1 data output value writing data to this register will reflect the data value on the corresponding port1 pin when it is configured as general purpose output pin. and writing data to re served bits is not effective. gpio port1 data input register (gpio_datain1) register address r/w description reset value gpio_datain1 0xfff8_301c r/w gpio port1 data input register 0xxxxx_xxxx free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 323 - revision a2 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved datain1[1:0] bits description [31:2] reserved - [1:0] datain1 port1 input data register the datain1 indicates the status of each gpio19~gpio18 pin regardless of its operation mode. t he reserved bits are read as 0s. gpio port2 configuration register (gpio_cfg2) register address r/w description reset value gpio_cfg2 0xfff8_3020 r/w gpio port2 configuration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pt2cfg9 pt2cfg8 15 14 13 12 11 10 9 8 pt2cfg7 pt2cfg6 pt2cfg5 pt2cfg4 7 6 5 4 3 2 1 0 pt2cfg3 pt2cfg2 pt2cfg1 pt2cfg0 *in the following pin definition, mark with shading is default function. 11 10 01 00 pt2cfg0 name type name type name type name type port2_0 reserved kpcol 0 i phy_rxerr i gpio20 i/o free datasheet http:///
W90N745cd/W90N745cdg - 324 - 11 10 01 00 pt2cfg1 name type name type name type name type port2_1 reserved kpcol1 i phy_crsdv i gpio21 i/o 11 10 01 00 pt2cfg2 name type name type name type name type port2_2 reserved kpcol2 i phy_rxd[0] i gpio22 i/o 11 10 01 00 pt2cfg3 name type name type name type name type port2_3 reserved kpcol3 i phy_rxd[1] i gpio23 i/o 11 10 01 00 pt2cfg4 name type name type name type name type port2_4 reserved kpcol4 i phy_refclk i gpio24 i/o 11 10 01 00 pt2cfg5 name type name type name type name type port2_5 reserved kpcol5 i phy_txen o gpio25 i/o 11 10 01 00 pt2cfg6 name type name type name type name type port2_6 reserved kpcol6 i phy_txd[0] o gpio26 i/o 11 10 01 00 pt2cfg7 name type name type name type name type port2_7 reserved kpcol7 i phy_txd[1] o gpio27 i/o 11 10 01 00 pt2cfg8 name type name type name type name type port2_8 reserved kprow 0 o phy_mdio i/o gpio28 i/o 11 10 01 00 pt2cfg9 name type name type name type name type port2_9 reserved kprow1 o phy_mdc o gpio29 i/o free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 325 - revision a2 gpio port2 direction register (gpio_dir2) register address r/w description reset value gpio_dir2 0xfff8_3024 r/w gpio port2 in/out direction control and pull-up enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved pupen2[9:8] 23 22 21 20 19 18 17 16 pupen2[7:0] 15 14 13 12 11 10 9 8 reserved omden2[9:8] 7 6 5 4 3 2 1 0 omden2[7:0] bits description [31:26] reserved - [25:16] pupen2 gpio29 ~ gpio20 port pin internal pull-up resister enable there are 10 bits for this register, the corresponding bit is set to ?1? will enable pull-up resister on io pin. 1 = enable 0 = disable after power on, the registers are disabled. [15:10] reserved - [9:0] omden2 gpio19 ~ gpio20 output mode enable 1 = output mode 0 = input mode note: output mode enable bits are valid only when bit pt2cfg9-0 is configured as general purpose i/o mode. each port pin can be enabled individually by setting the corresponding control bit. free datasheet http:///
W90N745cd/W90N745cdg - 326 - pgpio port2 data output register (gpio_dataout2) register address r/w description reset value gpio_dataout2 0xfff8_3028 r/w gpio port2 data output register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved dataout2[9:8] 7 6 5 4 3 2 1 0 dataout2[7:0] bits description [31:10] reserved - [9:0] dataout2 port2 data output value writing data to this register will reflect the data value on the corresponding port2 pin when it is configured as general purpose output pin. and writing data to reserved bits is not effective. gpio port2 data input register (gpio_datain2) register address r/w description reset value gpio_datain2 0xfff8_302c r/w gpio port2 data input register 0xxxxx_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved datain2[9:8] 7 6 5 4 3 2 1 0 datain2[7:0] free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 327 - revision a2 bits description [31:10] reserved - [9:0] datain2 port2 input data register the datain2 indicates the status of each gpio18~gpio27 pin regardless of its operation mode. the reserved bits will be read as 0s. gpio port4 configuration register (gpio_cfg4) register address r/w description reset value gpio_cfg4 0xfff8_3040 r/w gpio port4 configuration register 0x0015_5555 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pt4cfg10 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved *in the following pin definition, mark with shading is default function. 11 10 01 00 pt4cfg10 name type name type name type name type port4_10 reserved nirq3 i nwait i gpio28 i/o free datasheet http:///
W90N745cd/W90N745cdg - 328 - gpio port4 direction register (gpio_dir4) register address r/w description reset value gpio_dir4 0xfff8_3044 r/w gpio port4 in/out direction control and pull-up enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved pupen4[ 10] reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved omden4 [10] reserved 7 6 5 4 3 2 1 0 reserved bits description [31:27] reserved - [26] pupen4 gpio28 pin internal pull-up resister enable there is 1 bit for this register, t he bit is set to ?1? will enable pull-up resister on io pin. 1 = enable 0 = disable after power on the pull-up resister is disabled [25:11] reserved - [10] omden4 gpio28 output mode enable 1 = enable 0 = disable note: output mode enable bits are valid only when bit pt4cfg10 is configured as general purpose i/o mode. each port pin can be enabled individually by setting the corresponding control bit. [9:0] reserved - free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 329 - revision a2 gpio port4 data output register (gpio_dataout4) register address r/w description reset value gpio_dataout4 0xfff8_3048 r/w gpio port4 data output register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved dataout4[10 ] reserved 7 6 5 4 3 2 1 0 reserved bits description [31:11] reserved - [10] dataout4 port4 data output value writing data to this register will reflect the data value on the corresponding port4 pin when it is configured as general purpose output pin. and writing data to re served bits is not effective. [9:0] reserved - gpio port4 data input register (gpio_datain4) register address r/w description reset value gpio_datain4 0xfff8_304c r/w gpio port4 data input register 0xxxxx_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved datain4[10] reserved 7 6 5 4 3 2 1 0 reserved free datasheet http:///
W90N745cd/W90N745cdg - 330 - bits description [31:11] reserved - [10:0] datain4 port4 input data register the datain4 indicates the status of gp io28 pin regardless of its operation mode. the reserved bits will be read as 0s [9:0] reserved - gpio port5 configuration register (gpio_cfg5) register address r/w description reset value gpio_cfg5 0xfff8_3050 r/w gpio port5 configuration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved pt5cfg12 23 22 21 20 19 18 17 16 pt5cfg11 pt5cfg10 pt5cfg9 pt5cfg8 15 14 13 12 11 10 9 8 pt5cfg7 pt5cfg6 pt5cfg5 pt5cfg4 7 6 5 4 3 2 1 0 pt5cfg3 pt5cfg2 pt5cfg1 pt5cfg0 *in the following pin definition, mark with shading is default function. 11 10 01 00 pt5cfg0 name type name type name type name type port5_0 reserved reserved txd0 o gpio5 i/o 11 10 01 00 pt5cfg1 name type name type name type name type port5_1 reserved reserved rxd0 i gpio6 i/o 11 10 01 00 pt5cfg2 name type name type name type name type port5_2 reserved reserved txd1 o gpio7 i/o free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 331 - revision a2 11 10 01 00 pt5cfg3 name type name type name type name type port5_3 reserved reserved rxd1 i gpio8 i/o 11 10 01 00 pt5cfg4 name type name type name type name type port5_4 ps2clk o cts1 i txd2 io gpio9 i/o continued 11 10 01 00 pt5cfg5 name type name type name type name type port5_5 ps2data i/o rts1 io rxd2 i gpio10 i/o 11 10 01 00 pt5cfg6 name type name type name type name type port5_6 timer0 o sfrm o scl0 i/o gpio11 i/o 11 10 01 00 pt5cfg7 name type name type name type name type port5_7 timer1 o ssptx d o sda0 i/o gpio12 i/o 11 10 01 00 pt5cfg8 name type name type name type name type port5_8 kprow2 o sspsclk o scl1 i/o gpio13 i/o 11 10 01 00 pt5cfg9 name type name type name type name type port5_9 kprow3 o ssprxd i/o sda1 i/o gpio14 i/o 11 10 01 00 pt5cfg10 name type name type name type name type port5_10 reserved usbpwren o nwdog o gpio15 i/o free datasheet http:///
W90N745cd/W90N745cdg - 332 - 11 10 01 00 pt5cfg11 name type name type name type name type port5_11 reserved reserved nirq0 i gpio16 i/o 11 10 01 00 pt5cfg12 name type name type name type name type port5_12 reserved usbovcur i nirq1 i gpio17 i/o gpio port5 direction register (gpio_dir5) register address r/w description reset value gpio_dir5 0xfff8_3054 r/w gpio port5 in/out direction control and pull-up enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved pupen5[12:8] 23 22 21 20 19 18 17 16 pupen5[7:0] 15 14 13 12 11 10 9 8 reserved omden5[12:8] 7 6 5 4 3 2 1 0 omden5[7:0] bits description [31:29] reserved - [28:16] pupen5 gpio17 ~ gpio5 port pin internal pull-up resister enable there are 13 bits for this register, the corresponding bit is set to ?1? will enable pull-up resister on io pin. 1 = enable 0 = disable after power on the pull-up resisters are disable. [15:13] reserved [12:0] outen5 gpio17 ~ gpio5 output mode enable 1 = output mode 0 = input mode note: output mode enable bits are valid only when bit pt5cfg12-0 is configured as general purpose i/o mode. each port pin can be enabled individually by setting the corresponding control bit. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 333 - revision a2 gpio port5 data output register (gpio_dataout5) register address r/w description reset value gpio_dataout5 0xfff8_3058 r/w gpio port5 data output register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved dataout5[12:8] 7 6 5 4 3 2 1 0 dataout5[7:0] bits description [31:13] reserved - [12:0] dataout5 port5 data output value writing data to this register will reflect the data value on the corresponding port5 pin when it is configured as general purpose output pin. and writing data to re served bits is not effective. gpio port5 data input register (gpio_datain5) register address r/w description reset value gpio_datain5 0xfff8_305c r/w gpio port5 data input register 0xxxxx_xxxx 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved datain5[12:8] 7 6 5 4 3 2 1 0 datain5[7:0] free datasheet http:///
W90N745cd/W90N745cdg - 334 - bits description [31:13] reserved - [12:0] datain5 port5 input data register the datain5 indicates the status of each gpio17~gpio5 pin regardless of its operation mode. the reserved bits will be read as 0s. gpio debounce control register (gpio_dbncecon) register address r/w description reset value gpio_dbncecon 0xfff8_3070 r/w gpio debounce control register 0xxxxx_xx00 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved dbclksel reserved dben1 dben0 bits description [31:7] reserved - [6:4] dbclksel debounce clock selection these 3 bits are used to select the clock rate for de-bouncer circuit. the relationship between the system clock hclk and the de-bounce clock tclk_bun is as follows: tclk_bun = hclk / 2 dbclksel [3:2] reserved - [1] dben1 debounce circuit enable for gpio17 (nirq1) 1 = enable 0 = disable [0] dben0 debounce circuit enable for gpio16 (nirq0) 1 = enable 0 = disable free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 335 - revision a2 gpio interrupt configuration register (gpio_xicfg) register address r/w description reset value gpio_xicfg 0xfff8_3074 r/w extend interr upt configure register 0xxxxx_xx00 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 enirq3 dbe3 istype3 enirq2 dbe2 istype2 bits description [31:8] reserved - [7] enirq3 enable nirq3 setting this bit 1 to enable nirq3. 1 = enable nirq3 0 = disable nirq3 the aic interrupt channel 31 is rese rved for nirq3 and nirq2 (wired-or), if this bit is set and nirq3 occur, then it will send an interrupt request signal into aic module. [6] dbe3 debounce circuit enable for nirq3 (alternative function of nwait pin) the nirq3 shares the same debounce circuit with nirq[3:0], software can configure debounce sampling time in gpio_debnce control register. dbe3 function is the same as dbe0 in gpio_dbence register. 1 = enable debounce 0 = disable debounce [5:4] istype3 nirq3 source type istype3 interrupt source type 2?b00 low level sensitive 2?b01 high level sensitive 2?b10 negative edge triggered 2?b11 positive edge triggered free datasheet http:///
W90N745cd/W90N745cdg - 336 - continued bits description [3] enirq2 enable nirq2 setting this bit 1 to enable nirq2 1 = enable nirq2 0 = disable nirq2 the aic interrupt channel 31 is rese rved for nirq3 and nirq2 (wire-or), if this bit is set and nirq2 occur, then it will send an interrupt request signal into aic module. [2] dbe2 debounce circuit enable for nirq2 (alternative function of gpio0 pin) 1 = enable debounce 0 = disable debounce the nirq2 shares the same debounce circuit with nirq[1:0], software can configure debounce sampling time in gpio_debnce control register. dbe2 function is the same as dbe0 in gpio_dbence register. [1:0] istype2 nirq2 source type istype2 interrupt source type 2?b00 low level sensitive 2?b01 high level sensitive 2?b10 negative edge triggered 2?b11 positive edge triggered free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 337 - revision a2 gpio interrupt status register (gpio_xistatus) register address r/w description reset value gpio_xistatus 0xfff8_3078 r/w extend inte rrupt status register 0xxxxx_xx00 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved nirq3 nirq2 bits description [31:2] reserved - [1] nirq3 interrupt 3 status when interrupt input is detected with istype3 triggered condition, this flag will be set. it must be cleared by software. 1 = interrupt nirq3 is detected. 0 = no interrupt [0] nirq2 interrupt 2 status when interrupt input is detected with istype2 triggered condition, this flag will be set. it must be cleared by software. 1 = interrupt nirq2 is detected. 0 = no interrupt free datasheet http:///
W90N745cd/W90N745cdg - 338 - 6.14 i 2 c interface i 2 c is a two-wire, bi-directional serial bus that pr ovides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi-master bus including collision detection and arbitration that prevents data co rruption if two or more masters attempt to control the bus simultaneously. serial, 8-bit oriented bi-directional data transfers can be made up to 100 kbit/s in standard-mode, up to 400 kbit/s in the fast-mode, or up to 3.4 mbit/s in the high-speed mode. only 100kbps and 400kbps modes are supported directly. for high-s peed mode special ios are needed. if these ios are available and used, then high-speed mode is also supported. data is transferred between a master and a sl ave synchronously to scl on the sda line on a byte- by-byte basis. each data byte is 8 bits long. there is one scl clock pulse for each data bit with the msb being transmitted first . an acknowledge bit follows each trans ferred byte. each bit is sampled during the high period of scl; t herefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). the i 2 c master core includes the following features: ? amba apb interface compatible ? compatible with philips i 2 c standard, support master mode ? multi master operation ? clock stretching and wait state generation ? provide multi-byte transmit operation, up to 4 bytes can be transmitted in a single transfer ? software programmable acknowledge bit ? arbitration lost interrupt, with automatic transfer cancellation ? start/stop/repeated st art/acknowledge generation ? start/stop/repeated start detection ? bus busy detection ? supports 7 bit addressing mode ? fully static synchronous design with one clock domain ? software mode i 2 c free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 339 - revision a2 6.14.1 i 2 c protocol normally, a standard communicati on consists of four parts: 1) start or repeated start signal generation 2) slave address transfer 3) data transfer 4) stop signal generation scl sda s or sr msb ack p or sr p sr lsb msb lsb 1 2 7 8 9 1 2 3 - 7 8 9 a6 a5 a4 - a1 a0 r/w d7 d6 d5 - d1 d0 nack ack figure 6.14.1 data transfer on the i 2 c-bus s slave address r/w a data a data a/a p '0'(write) data transfer (n bytes + acknowledge) from master to slave from slave to master a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition a master-transmitter addressing a sl ave receiver with a 7-bit address the transfer direction is not changed '1'(read) data transfer (n bytes + acknowledge) s slave address r/w a data a data a p a master reads a slave immediately after the first byte (address) free datasheet http:///
W90N745cd/W90N745cdg - 340 - start or repeated start signal when the bus is free/idle, meaning no master dev ice is engaging the bus (both scl and sda lines are high), a master can initiate a transfer by sending a start signal. a start signal, usually referred to as the s-bit , is defined as a high to low transition on the sda line while scl is high . the start signal denotes the beginning of a new data transfer. a repeated start (sr) is a start signal without fi rst generating a stop signal. the master uses this method to communicate with another slave or the same slave in a different transfer direction (e.g. from writing to a device to reading from a device) without releasing the bus. the i 2 c core generates a start signal when the start bit in the command register (cmdr) is set and the read or write bits are also set. depending on the current status of the scl line, a start or repeated start is generated. stop signal the master can terminate the communication by generating a stop signal. a stop signal, usually referred to as the p-bit , is defined as a low to high transition on the sda line while scl is high . start condition stop condition scl sda start and stop conditions slave address transfer the first byte of data transferred by the master immediately after the start signal is the slave address. this is a 7-bits calling address followed by a rw bit. the rw bit signals the slave the data transfer direction. no two slaves in the system can have the same address. only the slave with an address that matches the one transmitted by the ma ster will respond by returning an acknowledge bit by pulling the sda low at the 9th scl clock cycle. the core treats a slave address transfer as any ot her write action. store the slave device?s address in the transmit register (txr) and set the write bit. the core will then transfer the slave address on the bus. msb lsb r/w a0 a1 a2 a3 a4 a5 a6 slave address the first byte after the start procedure free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 341 - revision a2 data transfer once successful slave addressing has been achiev ed, the data transfer can proceed on a byte-by- byte basis in the direction specif ied by the rw bit sent by the master. each transferred byte is followed by an acknowledge bit on the 9th scl clock cycle. if the slave signals a not acknowledge (nack) , the master can generate a stop signal to abort the data transfer or generate a repeated start signal and start a new transfer cycle. if the master, as the receiving device, does not acknowledge (nack) the slave, the slave releases the sda line for the master to generate a stop or repeated start signal. to write data to a slave, store the data to be tr ansmitted in the transmit register (txr) and set the write bit. to read data from a slave, set the read bit. during a transfer the core set the i 2 c_tip flag, indicating that a transfer is in progress . when the transfer is done the i 2 c_tip flag is cleared, the if flag set if enabled, then an interrupt generated. the receive register (rxr) contains valid data after the if flag has been set. the software ma y issue a new write or read command when the i 2 c_tip flag is cleared. data line stable; data valid change of data allowed scl sda bit transfer on the i 2 c-bus 12 89 scl from master data output by transmitter data output by receiver s start condition clock pulse for acknowledgement not acknowledge acknowledge acknowledge on the i 2 c-bus free datasheet http:///
W90N745cd/W90N745cdg - 342 - 6.14.2 i 2 c serial interface control registers map r : read only, w : write only, r/w : both read and write note1: the reset value of i 2 c_wr0/1 is 0x3f only when scr, sdr and ser are connected to pull high resistor. register address r/w description reset value i 2 c interface 0 i 2 c_csr0 0xfff8_6000 r/w i 2 c0 control and status register 0x0000_0000 i 2 c_divider0 0xfff8_6004 r/w i 2 c0 clock prescale register 0x0000_0000 i 2 c_cmdr0 0xfff8_6008 r/w i 2 c0 command register 0x0000_0000 i 2 c_swr0 0xfff8_600c r/w i 2 c0 software mode control register 0x0000_003f i 2 c_rxr0 0xfff8_6010 r i 2 c0 data receive register 0x0000_0000 i 2 c_txr0 0xfff8_6014 r/w i 2 c0 data transmit register 0x0000_0000 i 2 c interface 1 i 2 c_csr1 0xfff8_6100 r/w i 2 c1 control and status register 0x0000_0000 i 2 c_divider1 0xfff8_6104 r/w i 2 c1 clock prescale register 0x0000_0000 i 2 c_cmdr1 0xfff8_6108 r/w i 2 c1 command register 0x0000_0000 i 2 c_swr1 0xfff8_610c r/w i 2 c1 software mode control register 0x0000_003f i 2 c_rxr1 0xfff8_6110 r i 2 c1 data receive register 0x0000_0000 i 2 c_txr1 0xfff8_6114 r/w i 2 c1 data transmit register 0x0000_0000 i 2 c control and status register 0/1 (i 2 c_csr0/1) register address r/w description reset value i 2 c_csr0 0xfff8_6000 r/w i 2 c control and status register 0 0x0000_0000 i 2 c_csr1 0xfff8_6100 r/w i 2 c control and status register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved i 2 c_rxack i 2 c_busy i 2 c_al i 2 c_tip 7 6 5 4 3 2 1 0 reserved tx_num reserved if ie i 2 c_en free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 343 - revision a2 bits descriptions [31:12] reserved reserved [11] i 2 c_rxac k received acknowledge from slave (read only) this flag represents acknowledge from the addressed slave. 0 = acknowledge received (ack). 1 = not acknowledge received (nack). [10] i 2 c_busy i 2 c bus busy (read only) 0 = after stop signal detected. 1 = after start signal detected. [9] i 2 c_al arbitration lost (read only) this bit is set when the i 2 c core lost arbitration. arbitration is lost when: a stop signal is detected, but no requested. the master drives sda high, but sda is low. [8] i 2 c_tip transfer in progress (read only) 0 = transfer complete. 1 = transferring data. note: when a transfer is in progress, you will not allow writing to any register of the i 2 c master core except swr. [5:4] tx_num transmit byte counts these two bits represent how many bytes are remained to transmit. when a byte has been transmitted, the tx_num will decrease 1 until all bytes are transmitted (tx_num = 0x0) or nack received from slave. then the interrupt signal will assert if ie was set. 0x0 = only one byte is left for transmission. 0x1 = two bytes are left to for transmission. 0x2 = three bytes are left for transmission. 0x3 = four bytes are left for transmission. [3] reserved reserved [2] if interrupt flag the interrupt flag is set when: transfer has been completed. transfer has not been completed, but slave responded nack (in multi-byte transmit mode). arbitration is lost. note: this bit is read only, but can be cleared by writing 1 to this bit. [1] ie interrupt enable 0 = disable i 2 c interrupt. 1 = enable i 2 c interrupt. [0] i 2 c_en i 2 c core enable 0 = disable i 2 c core, serial bus outputs ar e controlled by sdw/scw. 1 = enable i 2 c core, serial bus outputs are controlled by i 2 c core. free datasheet http:///
W90N745cd/W90N745cdg - 344 - i 2 c prescale register 0/1 (i 2 c_divider 0 /1) register address r/w description reset value i 2 c_divider0 0xfff8_6004 r/w i 2 c clock prescale register 0 0x0000_0000 i 2 c_divider1 0xfff8_6104 r/w i 2 c clock prescale register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 divider[15:8] 7 6 5 4 3 2 1 0 divider[7:0] bits descriptions [15:0] divider clock prescale register it is used to prescale the scl clock line. due to the structure of the i 2 c interface, the core uses a 5*scl clock internally. the prescale register must be programmed to this 5*scl frequency (minus 1). change the value of the prescale register only when the ?i 2 c_en? bit is cleared. example: pclk = 32mhz, desired scl = 100khz ) ( 3 ) ( 63 1 100 5 32 hex f dec khz mhz prescale = = ? ? = free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 345 - revision a2 i 2 c command register 0/1 (i 2 c_cmdr 0/1) register address r/w description reset value i 2 c_cmdr0 0xfff8_6008 r/w i 2 c command register 0 0x0000_0000 i 2 c_cmdr1 0xfff8_6108 r/w i 2 c command register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved start stop read write ack note: software can write this register only when i 2 c_en = 1. bits descriptions [31:5] reserved reserved [4] start generate start condition generate (repeated) start condition on i 2 c bus. [3] stop generate stop condition generate stop condition on i 2 c bus. [2] read read data from slave retrieve data from slave. [1] write write data to slave transmit data to slave. [0] ack send acknowledge to slave when i 2 c behaves as a receiver, sent ac k (ack = ?0?) or nack (ack = ?1?) to slave. note: the start, stop, read and write bits are cleared automat ically while transfer finished. read and write cannot be set concurrently. free datasheet http:///
W90N745cd/W90N745cdg - 346 - i 2 c software mode register 0/1(i 2 c_swr 0/1) register address r/w description reset value i 2 c_swr0 0xfff8_600c r/w i 2 c software mode control register 0 0x0000_003f i 2 c_swr1 0xfff8_610c r/w i 2 c software mode control register 1 0x0000_003f 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved reserved sdr scr reserved sdw scw note: this register is used as software mode of i 2 c. software can read/write this register no matter i 2 c_en is 0 or 1. but scl and sda are controlled by software only when i 2 c_en = 0. bits descriptions [31:6] reserved reserved [5] reserved reserved [4] sdr serial interface sda status (read only) 0 = sda is low . 1 = sda is high . [3] scr serial interface sck status (read only) 0 = scl is low . 1 = scl is high . [2] reserved reserved [1] sdw serial interface sda output control 0 = sda pin is driven low . 1 = sda pin is tri-state . [0] scw serial interface sck output control 0 = scl pin is driven low . 1 = scl pin is tri-state . free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 347 - revision a2 i 2 c data receive register 0/1 (i 2 c_rxr 0/1) register offset r/w description reset value i 2 c_rxr0 0xfff8_6010 r i 2 c data receive register 0 0x0000_0000 i 2 c_rxr1 0xfff8_6110 r i 2 c data receive register 1 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rx [7:0] bits descriptions [31:8] reserved reserved [7:0] rx data receive register the last byte received via i 2 c bus will put on this register. the i 2 c core only used 8-bit receive buffer. free datasheet http:///
W90N745cd/W90N745cdg - 348 - i 2 c data transmit register 0/1 (i 2 c_txr 0/1) register address r/w description reset value i 2 c_txr0 0xfff8_6014 r/w i 2 c data transmit register 0x0000_0000 i 2 c_txr1 0xfff8_6114 r/w i 2 c data transmit register 0x0000_0000 31 30 29 28 27 26 25 24 tx [31:24] 23 22 21 20 19 18 17 16 tx [23:16] 15 14 13 12 11 10 9 8 tx [15:8] 7 6 5 4 3 2 1 0 tx [7:0] bits descriptions [31:0] tx data transmit register the i 2 c core used 32-bit transmit buffer and provide multi-byte transmit function. set csr[tx_num] to a value that you want to transmit. i 2 c core will always issue a transfer from the highest byte first. for example, if csr[tx _num] = 0x3, tx[31:24] will be transmitted first, then tx[23:16], and so on. in case of a data transfer, all bits will be treated as data. in case of a slave address transfer, the first 7 bits will be treated as 7- bit address and the lsb represent the r/w bit. in this case, lsb = 1, reading from slave lsb = 0, writing to slave free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 349 - revision a2 6.15 universal serial interface the usi is a synchronous serial interface performs a serial-to-parallel conversion on data characters received from the peripheral, and a parallel-to-ser ial conversion on data characters received from cpu. it can generate an interrupt signal when data tr ansfer is finished and can be cleared by writing 1 to the interrupt flag. the active level of device/sl ave select signal can be chosen to low active or high active, which depends on the peripheral it?s connected. writing a divisor into divider register can program the frequency of serial clock output. this ma ster core contains four 32-bit transmit/receive buffers, and can provide burst mode operation. the maximum bits can be transmitted/received is 32 bits, and can transmit/receive dat a up to four times successive. the usi (microwire/spi) master co re includes the following features: ? amba apb interface compatible ? support usi (microwire/spi) master mode ? full duplex synchronous serial data transfer ? variable length of transfer word up to 32 bits ? provide burst mode operation, transmit/receive can be executed up to four times in one transfer ? msb or lsb first data transfer ? rx and tx on both rising or falli ng edge of serial clock independently ? 1 slave/device select lines ? fully static synchronous design with one clock domain free datasheet http:///
W90N745cd/W90N745cdg - 350 - 6.15.1 usi timing diagram the timing diagram of usi is shown as following. msb (tx[7]) lsb (tx[0]) msb (rx[7]) lsb (rx[0]) mw_ss_o mw_sclk_o mw_so_o mw_si_i cntrl[lsb]=0, cntrl[tx_num]=0x 0, cntrl[tx_bit_len]=0x08, cntrl[tx_neg]=1, cntrl[r x_neg]=0, ssr[ss_lvl]=0 tx[6] tx[5] tx[4] tx[3] tx[2] tx[1] rx[6] rx[5] rx[4] rx[3] rx[2] rx[1] figure 6.15.1 usi timing mw_ss_o mw_sclk_o mw_so_o mw_si_i cntrl[lsb]=1, cntrl[tx_num]= 0x0, cntrl[tx_bit_len]=0x08, cntrl[tx_neg]=0, cntrl[rx_neg]=1, ssr[ss_lvl]=0 msb (tx[7]) lsb (tx[0]) msb (rx[7]) lsb (rx[0]) tx[1] tx[2] tx[3] tx[4] tx[5] tx[6] rx[1] rx[2] rx[3] rx[4] rx[5] rx[6] figure 6.15.2 alternate phase sclk clock timing free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 351 - revision a2 6.15.2 usi registers map r : read only, w : write only, r/w : both read and write register address r/w description reset value usi_cntrl 0xfff8_6200 r/w contro l and status register 0x0000_0004 usi_divider 0xfff8_6204 r/w clo ck divider register 0x0000_0000 usi_ssr 0xfff8_6208 r/w slave select register 0x0000_0000 reserved 0xfff8_620c n/a reserved n/a usi_rx0 0xfff8_6210 r data receive register 0 0x0000_0000 usi_rx1 0xfff8_6214 r data receive register 1 0x0000_0000 usi_rx2 0xfff8_6218 r data receive register 2 0x0000_0000 usi_rx3 0xfff8_621c r data receive register 3 0x0000_0000 usi_tx0 0xfff8_6210 w data transmit register 0 0x0000_0000 usi_tx1 0xfff8_6214 w data transmit register 1 0x0000_0000 usi_tx2 0xfff8_6218 w data transmit register 2 0x0000_0000 usi_tx3 0xfff8_621c w data transmit register 3 0x0000_0000 note 1: when software programs cntrl, the go_busy bit should be written last. free datasheet http:///
W90N745cd/W90N745cdg - 352 - usi_control and status register (usi_cntrl) register address r/w description reset value usi_cntrl 0xfff8_6200 r/w usi control and status register 0x0000_0004 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved ie if 15 14 13 12 11 10 9 8 sleep reserved lsb tx_num 7 6 5 4 3 2 1 0 tx_bit_len tx_neg rx_neg go_busy bits descriptions [31:18] reserved reserved [17] ie interrupt enable 0 = disable usi interrupt. 1 = enable usi interrupt. [16] if interrupt flag 0 = it indicates that the transfer dose not finish yet. 1 = it indicates that the transfer is done. the interrupt flag is set if it was enable. note: this bit is read only, but can be cleared by writing 1 to this bit. [15:12] sleep suspend interval these four bits provide the confi guration of suspend interval between two successive transmit/receive in a transfer. the default value is 0x0. when cntrl [tx_num] = 00, setting this field has no effect on transfer. the desired interval is obtained according to the following equation (from the last falling edge of current sclk to the first rising edge of next sclk): (cntrl[sleep] + 2)*period of sclk sleep = 0x0 ? 2 sclk clock cycle sleep = 0x1 ? 3 sclk clock cycle ?? sleep = 0xe ? 16 sclk clock cycle sleep = 0xf ? 17 sclk clock cycle free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 353 - revision a2 continued bits descriptions [11] reserved reserved [10] lsb send lsb first 0 = the msb is transmitted/received first (which bit in txx/rxx register that is depends on the tx_bit_len field in the cntrl register). 1 = the lsb is sent first on the line (bit txx[0]), and the first bit received from the line will be put in t he lsb position in the rx register (bit rxx[0]). [9:8] tx_num transmit/receive numbers this field specifies how many transmit/receive numbers should be executed in one transfer. 00 = only one transmit/receive w ill be executed in one transfer. 01 = two successive transmit/receive will be executed in one transfer. 10 = three successive transmit/receive will be executed in one transfer. 11 = four successive transmit/recei ve will be executed in one transfer. [7:3] tx_bit_len transmit bit length this field specifies how many bits are transmitted in one transmit/receive. up to 32 bits can be transmitted. tx_bit_len = 0x01 ? 1 bit tx_bit_len = 0x02 ? 2 bits ?? tx_bit_len = 0x1f ? 31 bits tx_bit_len = 0x00 ? 32 bits [2] tx_neg transmit on negative edge 0 = the mw_so_o signal is changed on the rising edge of mw_sclk_o. 1 = the mw_so_o signal is changed on the falling edge of mw_sclk_o. [1] rx_neg receive on negative edge 0 = the mw_si_i signal is latched on the rising edge of mw_sclk_o. 1 = the mw_si_i signal is latched on the falling edge of mw_sclk_o. [0] go_busy go and busy status 0 = writing 0 to this bit has no effect. 1 = writing 1 to this bit starts the transfer. this bit remains set during the transfer and is automatically cleared after transfer finished. note: all registers should be set before writing 1 to the go_busy bit in the cntrl register. when a transfer is in progress, writing to any register of the usi(microwire/ spi) master core has no effect. free datasheet http:///
W90N745cd/W90N745cdg - 354 - usi divider register (usi_divider) register address r/w description reset value usi_divider 0xfff8_6204 r/w usi clock divider register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 divider[15:8] 7 6 5 4 3 2 1 0 divider[7:0] bits descriptions [15:0] divider clock divider register the value in this field is the frequenc y divider of the system clock pclk to generate the serial clock on t he output mw_sclk_o. the desired frequency is obtained according to the following equation: () 2 * 1 + = divider f f pclk sclk note: suggest divider should be at least 1. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 355 - revision a2 usi slave select register (usi_ssr) register address r/w description reset value usi_ssr 0xfff8_6208 r/w usi slave select register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved ass ss_lvl ssr[1:0] bits descriptions [3] ass automatic slave select 0 = if this bit is cleared, slave select signals are asserted and de- asserted by setting and clearing related bits in ssr register. 1 = if this bit is set, mw_ss_o signals are generated automatically. it means that device/slave select signal, which is set in ssr register is asserted by the usi controller when transmit/receive is started by setting cntrl[go_busy], and is de-asserted after every transmit/receive is finished. [2] ss_lvl slave select active level it defines the active level of dev ice/slave select signal (mw_ss_o). 0 = the mw_ss_o slave select signal is active low . 1 = the mw_ss_o slave select signal is active high . [1:0] ssr slave select register if ssr[ass] bit is cleared, writing 1 to any bit location of this field sets the proper mw_ss_o line to an active state and writing 0 sets the line back to inactive state. if ssr[ass] bit is set, writing 1 to any bit location of this field will select appropriate mw_ss_o line to be automatic ally driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (the active level of mw_ss_o is specified in ssr[ss_lvl]). note: this interface can only drive one device/slave at a given time. therefore, the slave select of t he selected device must be set to its active level before starting any read or write transfer. free datasheet http:///
W90N745cd/W90N745cdg - 356 - usi data receive register 0/1/2/3 (usi_rx0/1/2/3) register address r/w description reset value usi_rx0 0xfff8_6210 r usi data receive register 0 0x0000_0000 usi_rx1 0xfff8_6214 r usi data receive register 1 0x0000_0000 usi_rx2 0xfff8_6218 r usi data receive register 2 0x0000_0000 usi_rx3 0xfff8_621c r usi data receive register 3 0x0000_0000 31 30 29 28 27 26 25 24 rx [31:24] 23 22 21 20 19 18 17 16 rx [23:16] 15 14 13 12 11 10 9 8 rx [15:8] 7 6 5 4 3 2 1 0 rx [7:0] bits descriptions [31:0] rx data receive register the data receive registers hold the value of received data of the last executed transfer. valid bits depend on the transmit bit length field in the cntrl register. for example, if cnt rl[tx_bit_len] is set to 0x08 and cntrl[tx_num] is set to 0x0, bit rx0[7:0] holds t he received data. note: the data receive registers are read only registers. a write to these registers will actually modify the data transmit registers because those registers share the same ffs. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 357 - revision a2 data transmit register 0/1/2/3 (tx0/1/2/3) register address r/w description reset value usi_tx0 0xfff8_6210 w usi data transmit register 0 0x0000_0000 usi_tx1 0xfff8_6214 w usi data transmit register 1 0x0000_0000 usi_tx2 0xfff8_6218 w usi data transmit register 2 0x0000_0000 usi_tx3 0xfff8_621c w usi data transmit register 3 0x0000_0000 31 30 29 28 27 26 25 24 tx [31:24] 23 22 21 20 19 18 17 16 tx [23:16] 15 14 13 12 11 10 9 8 tx [15:8] 7 6 5 4 3 2 1 0 tx [7:0] bits descriptions [31:0] tx data transmit register the data transmit registers hold the data to be transmitted in the next transfer. valid bits depend on the transmit bit length field in the cntrl register. for example, if cntrl[t x_bit_len] is set to 0x08 and the cntrl[tx_num] is set to 0x0, the bi t tx0[7:0] will be transmitted in next transfer. if cntrl[tx_bit_len] is set to 0x00 and cntrl[tx_num] is set to 0x3, the core will perform f our 32-bit transmit/receive successive using the same setting (the order is tx0[31:0], tx1[31:0], tx2[31:0], tx3[31:0]). note: the rxx and txx registers share the same flip-flops, which means that what is received from the input data line in one transfer will be transmitted on the output data line in the next transfer if no write access to the txx register is executed between the transfers. free datasheet http:///
W90N745cd/W90N745cdg - 358 - 6.16 pwm the W90N745 have 4 channels pwm timers. they c an be divided into two groups. each group has 1 prescaler, 1 clock divider, 2 clock selectors, 2 16-bit counters, 2 16-bit comparators, 1 dead-zone generator. they are all driven by pclk (80 mhz) . each channel can be used as a timer and issue interrupt independently. two channels pwm timers in one group share the sa me prescaler. clock divider provides each channel with 5 clock sources (1, 1/2, 1/4, 1/8, 1/16). each channel re ceives its own clock signal from clock divider which receives clock from 8-bit pr escaler. the 16-bit counter in each channel receive clock signal from clock selector and can be used to handle one pwm period. the 16-bit comparator compares number in counter with threshold number in register loaded previously to generate pwm duty cycle. the clock signal from clock divider is called pw m clock. dead-zone generator utilize pwm clock as clock source. once dead-zone generator is enabl ed, output of two pwm timer in one group is blocked. two output pin are all used as dead-zone generator output signal to control off-chip power device. to prevent pwm driving output pi n with unsteady waveform, 16-bit counter and 16-bit comparator are implemented with double buffering feature. user can f eel free to write data to counter buffer register and comparator buffer register without generating glitch. when 16-bit down counter reaches zero, the interrupt request is generated to inform cpu that time is up. when counter reaches zero, if counter is set as toggle mode, it is rel oaded automatically and start to generate next cycle. user can set counter as one-shot mode instead of toggle mode. if counter is set as one-shot mode, counter will stop and generat e one interrupt request when it reaches zero. the value of comparator is used for pulse width modulation. the counter control logic changes the output level when down-counter value matc hes the value of compare register. the pwm timer features are shown as below: z two 8-bit prescalers and two clock dividers z four clock selectors z four 16-bit counters and four 16-bit comparators z two dead-zone generator free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 359 - revision a2 6.16.1 pwm double buffering and reload automatically W90N745 pwm timers have a double buffering func tion, enabling the reload value changed for next timer operation without stopping curr ent timer operation. although new timer value is set, current timer operation still operate successfully. the counter value can be written into pwm_cnr0, pwm_cnr1, pwm_cnr2, pwm_cnr3 and current counter value can be read from pw m_pdr0, pwm_pdr1, pwm_pdr2, pwm_pdr3. the auto-reload operation copies from pwm_cnr0, pwm_cnr1, pwm_cnr2, pwm_cnr3 to down-counter when down-counter r eaches zero. if pwm_cnr0~3 are set as zero, counter will be halt when counter count to zero. if auto-reload bit is set as zero, counter will be stopped immediately. 6.16.2 modulate duty ratio the double buffering function allows cmr written at any point in current cycle. the loaded value will take effect from next cycle. free datasheet http:///
W90N745cd/W90N745cdg - 360 - 6.16.3 dead zone generator W90N745 pwm is implemented with dead zone generator. they are built for power device protection. this function enables generation of a programmable time gap at the rising of pwm output waveform. user can program pwm_ppr [31: 24] and pwm_ppr [23:16] to determine the dead zone interval. dead zone generator operation pwm_out1 pwm_out1_n pwm_out1_dz pwm_out1_n_dz dead zone interval 6.16.4 pwm timer start procedure 1. setup clock selector (pwm_csr) 2. setup prescaler & dead zone interval (pwm_ppr) 3. setup inverter on/off, dead zone generator on/off, toggle mode /one-shot mode, and pwm timer off. (pwm_pcr) 4. setup comparator register (pwm_cmr) 5. setup counter register (pwm_cnr) 6. setup interrupt enable register (pwm_pier) 7. enable pwm timer (pwm_pcr) 6.16.5 pwm timer stop procedure method 1 : set 16-bit down counter(pwm_cnr) as 0, and monitor pwm_pdr. when pwm_pdr reaches to 0, disable pwm timer (pwm_pcr). (recommended) method 2 : set 16-bit down counter(pwm_cnr) as 0. when interrupt request happen, disable pwm timer (pwm_pcr). (recommended) method 3 : disable pwm timer directly (pwm_pcr). (not recommended) free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 361 - revision a2 6.16.6 pwm register map register address r/w description reset value pwm_ppr 0xfff8_7000 r/w pwm prescaler register 0x0000_0000 pwm_csr 0xfff8_7004 r/w pwm clo ck select register 0x0000_0000 pwm_pcr 0xfff8_7008 r/w pwm control register 0x0000_0000 pwm_cnr0 0xfff8_700c r/w pwm counter register 0 0x0000_0000 pwm_cmr0 0xfff8_7010 r/w pwm comparator register 0 0x0000_0000 pwm_pdr0 0xfff8_7014 r pwm data register 0 0x0000_0000 pwm_cnr1 0xfff8_7018 r/w pwm counter register 1 0x0000_0000 pwm_cmr1 0xfff8_701c r/w pwm comparator register 1 0x0000_0000 pwm_pdr1 0xfff8_7020 r pwm data register 1 0x0000_0000 pwm_cnr2 0xfff8_7024 r/w pwm counter register 2 0x0000_0000 pwm_cmr2 0xfff8_7028 r/w pwm comparator register 2 0x0000_0000 pwm_pdr2 0xfff8_702c r pwm data register 2 0x0000_0000 pwm_cnr3 0xfff8_7030 r/w pwm counter register 3 0x0000_0000 pwm_cmr3 0xfff8_7034 r/w pwm comparator register 3 0x0000_0000 pwm_pdr3 0xfff8_7038 r pwm data register 3 0x0000_0000 pwm_pier 0xfff8_703c r/w pwm in terrupt enable register 0x0000_0000 pwm_piir 0xfff8_7040 r/c pwm interr upt indication register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 362 - pwm prescaler register (pwm_ppr) register address r/w description reset value pwm_ppr 0xfff8_7000 r/w pwm prescaler register 0x0000_0000 31 30 29 28 27 26 25 24 dzi1 23 22 21 20 19 18 17 16 dzi0 15 14 13 12 11 10 9 8 cp1 7 6 5 4 3 2 1 0 cp0 bits descriptions [31:24] dzi1 dzi1: dead zone interval register 1, these 8-bit determine dead zone length. the 1 unit time of dead zone length is received from clock selector 2. [23:16] dzi0 dzi0: dead zone interval register 0, these 8-bit determine dead zone length. the 1 unit time of dead zone length is received from clock selector 0. [15:8] cp1 cp1 : clock prescaler 1 for pwm timer channel 2 & 3 clock input is divided by (cp1 + 1) bef ore it is fed to the counter. 2 & 3 if cp1=0, then the prescaler 1 output clock will be stopped. [7:0] cp0 cp0 : clock prescaler 0 for pwm timer channel 0 & 1 clock input is divided by (cp0 + 1) bef ore it is fed to the counter. 0 & 1 if cp0=0, then the prescaler 0 output clock will be stopped. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 363 - revision a2 pwm clock select register (pwm_csr) register address r/w description reset value pwm_csr 0xfff8_7004 r/w pwm clock select register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved csr3 reserved csr2 7 6 5 4 3 2 1 0 reserved csr1 reserved csr0 bits descriptions [14:12] csr3 select clock input for channel 3 [10:8] csr2 select clock input for channel 2. [6:4] csr1 select clock input for channel 1 [2:0] csr0 select clock input for channel 0 csr3 input clock divided by 000 2 001 4 010 8 011 16 100 1 free datasheet http:///
W90N745cd/W90N745cdg - 364 - pwm control register (pwm_pcr) register address r/w description reset value pwm_pcr 0xfff8_7008 r/w pwm control register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved pcr19 pcr18 pcr17 pcr16 15 14 13 12 11 10 9 8 pcr15 pcr14 pcr13 pcr12 pcr11 pcr10 pcr09 pcr08 7 6 5 4 3 2 1 0 pcr07 pcr06 pcr05 pcr04 pcr03 pcr02 pcr01 pcr00 bits descriptions [19] pcr 19 channel 3 toggle/one shot mode 1 = toggle mode 0 = one shot mode [18] pcr 18 channel 3 inverter on/off 1 = inverter on 0 = inverter off [17] pcr 17 reserved [16] pcr 16 channel 3 enable/disable 1 = enable 0 = disable [15] pcr 15 channel 2 toggle/one shot mode 1 = toggle mode 0 = one shot mode [14] pcr 14 channel 2 inverter on/off 1 = inverter on 0 = inverter off [13] pcr 13 reserved free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 365 - revision a2 continued bits descriptions [12] pcr 12 channel 2 enable/disable 1 = enable 0 = disable [11] pcr 11 channel 1 toggle/one shot mode 1 = toggle mode 0 = one shot mode [10] pcr 10 channel 1 inverter on/off 1 = inverter on 0 = inverter off [09] pcr 09 reserved [08] pcr 08 channel 1 enable/disable 1 = enable 0 = disable [07] pcr 07 reserved [06] pcr 06 reserved [05] pcr 05 dead-zone generator 1 enable/disable 1 = enable dead-zone generator 0 = disable dead-zone generator [04] pcr 04 dead-zone generator 0 enable/disable 1 = enable dead-zone generator 0 = disable dead-zone generator [03] pcr 03 channel 0 toggle/one shot mode 1 = toggle mode 0 = one shot mode [02] pcr 02 channel 0 inverter on/off 1 = inverter on 0 = inverter off [01] pcr 01 reserved [00] pcr 00 channel 0 enable/disable 1 = enable 0 = disable free datasheet http:///
W90N745cd/W90N745cdg - 366 - pwm counter register 0/1/2/3 (pwm_cnr0/1/2/3) register address r/w description reset value pwm_cnr0 0xfff8_700c r/w pwm counter register 0 0x0000_0000 pwm_cnr1 0xfff8_7018 r/w pwm counter register 1 0x0000_0000 pwm_cnr2 0xfff8_7024 r/w pwm counter register 2 0x0000_0000 pwm_cnr3 0xfff8_7030 r/w pwm counter register 3 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 cnrx[15:8] 7 6 5 4 3 2 1 0 cnrx[7:0] bits descriptions [31:16] reserved - [15:0] cnrx cnr: pwm counter/timer buffer. inserted data range: 65535~0. unit: 1 pwm clock cycle note 1: one pwm counter countdown interval = cnr + 1.if cnr is loaded as zero, pwm counter will be stopped. note 2: programmer can feel free to write data to cnr at any time, and it will be reloaded when pwm counter reaches zero. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 367 - revision a2 pwm comparator register 0/1/2/3 (pwm_cmr0/1/2/3) register address r/w description reset value pwm_cmr0 0xfff8_7010 r/w pwm comparator register 0 0x0000_0000 pwm_cmr1 0xfff8_701c r/w pwm comparator register 1 0x0000_0000 pwm_cmr2 0xfff8_7028 r/w pwm comparator register 2 0x0000_0000 pwm_cmr3 0xfff8_7034 r/w pwm comparator register 3 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 cmrx[15:8] 7 6 5 4 3 2 1 0 cmrx[7:0] bits descriptions [31:16] reserved - [15:0] cmrx cmr: pwm comparator register inserted data range: 65535~0. cmr is used to determine pwm output duty ratio. note 1: pwm duty = cmr + 1.if cmr is loaded as zero, pwm duty = 1 note 2: programmer can feel free to write data to cmr at any time, and it will be reloaded when pwm counter reaches zero. free datasheet http:///
W90N745cd/W90N745cdg - 368 - pwm data register 0/1/ 2/3 (pwm_pdr 0/1/2/3) register address r/w description reset value pwm_pdr0 0xfff8_7014 r pwm data register 0 0x0000_0000 pwm_pdr1 0xfff8_7020 r pwm data register 1 0x0000_0000 pwm_pdr2 0xfff8_702c r pwm data register 2 0x0000_0000 pwm_pdr3 0xfff8_7038 r pwm data register 3 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 pdrx[15:8] 7 6 5 4 3 2 1 0 pdrx[7:0] bits descriptions [31:16] reserved - [15:0] pdrx pdr: pwm data register. user can monitor pdr to get current value in 16-bit down counter. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 369 - revision a2 pwm interrupt enable register (pwm_pier) register address r/w description reset value pwm_pier 0xfff8_703c r/w pwm interrupt enable register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved pier3 pier2 pier1 pier0 bits descriptions [31:4] reserved - [3] pier3 enable/disable pwm counter channel 3 interrupt request 1 = enable 0 = disable [2] pier2 enable/disable pwm counter channel 2 interrupt request 1 = enable 0 = disable [1] pier1 enable/disable pwm counter channel 1 interrupt request 1 = enable 0 = disable [0] pier0 enable/disable pwm counter channel 0 interrupt request 1 = enable 0 = disable free datasheet http:///
W90N745cd/W90N745cdg - 370 - pwm interrupt indication register (pwm_piir) register address r/w/c description reset value pwm_piir 0xfff8_7040 r/c pwm interrupt indication register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved piir3 piir2 piir1 piir0 bits descriptions [3] piir3 pwm counter channel 3 interrupt flag [2] piir2 pwm counter channel 2 interrupt flag [1] piir1 pwm counter channel 1 interrupt flag [0] piir0 pwm counter channel 0 interrupt flag note: user can clear each interrupt flag by writing a zero to corresponding bit in piir free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 371 - revision a2 6.17 keypad interface W90N745 keypad interface ( kpi ) is an apb slave with 4-row scan output and 8-column scan input. kpi scans an array up to 16x8 with an external 4 to 16 decoder. it can also be programmed to scan 8x8 or 4x8 key array. if the 4x8 array is select ed then external decoder is not necessary because the scan signals are dived by W90N745 itself. for mini mum pin counts application, an auxiliary priority encoder (ttl 74148) can be used to encode 8 columns input to 3 binary code and one indicator flag. total 8 pins are required to implement 16x8 key scan. any 1 or 2 keys in the array that press ed are debounced and encoded. the keypad controller scan key matrix from row0 col 0 ? 1 ? 2 ?. ? 7, row1 col 0 ? 1 ? 2 ? ? 7 till to row 16 (or row 8 or row 4) col 0 ? 0 ? 1 ?. ? 7. if more than 2 keys are pressed, only the keys or apparent keys in the array with the lowest address will be decoded. kpi also supports 2-keys scan interrupt and specified 3-keys interrupt or chip reset. if the 3 pressed keys matches with the 3 keys defined in kpi3kconf , it will generate an interrupt or chip reset to nwdog reset output depend on the enrst setting. the interrupt is generated whenever the scanner detects a key is pressed. the interrupt conditions are 1 key, 2 keys and 3keys. W90N745 provides one keypad connecting interface. t he interface is in ethernet rmii phy interface and i 2 c interface 2 sda1, scl1 (gpio18-27). softwar e should set kpsel bit to ?0? in kpiconf register to select mac phy inte rface for connecting keypad matrix. the keypad interface has the following features: z maximum 16x8 array z programmable debounce time z low-power wakeup mode z programmable three-key reset free datasheet http:///
W90N745cd/W90N745cdg - 372 - figure 6.17.1 W90N745 keypad interface 6.17.1 keypad interface register map register address r/w description reset value kpiconf 0xfff8_8000 r/w keypad controller configuration register 0x0000_0000 kpi3kconf 0xfff8_8004 r/w keypad controller 3-keys configuration register 0x0000_0000 kpilpconf 0xfff8_8008 r/w keypad controller low power configuration register 0x0000_0000 kpistatus 0xfff8_800c r/o keypad c ontroller status register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 373 - revision a2 6.17.2 register description keypad controller configurat ion register (kpi_conf) register address r/w description reset value kpiconf 0xfff8_8000 r/o key pad c onfiguration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved encode oden kpsel enkp ksize 15 14 13 12 11 10 9 8 dbtc 7 6 5 4 3 2 1 0 prescale bits description [31:22] reserved - [21] encode enable encode function if an auxiliary 8 to 3 encoder is used to minimize keypad interface pin counts, user can connect encoder data to kpi_col[2:0] and indicator flag (low active) to kpi_col[3]. 1 = enable encoder function 0 = default. (8 column inputs) [20] oden open drain enable if there are more than one key are pressed in the same column, then ?short-circuit? will appear between acti ve scan and inactive scan row. software can set this bit high to enable scan output kpi_row[3:0] pins work as ?open-drain? to avoid the ?short-circuit?. 1 = open drain 0 = push-pull driver [19] kpsel key pad select software should set this bit to ?0? to select mac phy interface for connecting keypad matrix. 0 = pin #53~55, #57~60, #62~65 #19 and #20 are used as keypad interface free datasheet http:///
W90N745cd/W90N745cdg - 374 - continued bits description [18] enkp key pad scan enable setting this bit high enable the key scan function. 1 = enable key pad scan 0 = disable key pad scan [17:16] ksize key array size ksize key array size 2?b00 4x8, 3x8, 2x8, 1x8 2?b01 8x8, 7x8, 6x8, 5x8 2?b1x 16x8, 15x8, 14x8, 13x 8, 12x8, 11x8, 10x8, 9x8 [15:8] dbtc debounce terminal count debounce counter counts the number of consecutive scans that decoded the same keys. when de-bounc e counter counter is equal to terminal count it will generate a key scan interrupt. [7:0] prescale row scan cycle pre-scale value this value is used to prescale row scan cycle. the prescale counter is clocked by 0.9375mhz clock. key array scan time = 1.067us x prescale x16 rows the following example is the scan time for prescale = 0xfa tscan_time = 1.067us x 250 x16 = 4.268ms if debounce terminal count = 0x05, key detection interrupt is fired in approximately 21.34ms. the array scan time can range from 17.07us to 1.118 sec. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 375 - revision a2 figure 6.17.2 keypad interface with row decoder and column encoder keypad controller 3-keys confi guration register (kpi3kconf) register address r/w description reset value kpi3kconf 0xfff8_8004 w/r three-key configuration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved en3ky enrst 23 22 21 20 19 18 17 16 reserved k32r k32c 15 14 13 12 11 10 9 8 reserved k31r k31c 7 6 5 4 3 2 1 0 reserved k30r k30c free datasheet http:///
W90N745cd/W90N745cdg - 376 - bits description [31:26] reserved - [25] en3ky enable three-keys detection setting this bit enables hardware to detect 3 keys specified by software [24] enrst enable three-key reset setting this bit enable hardware rese t when three-key is detected. en3ky enrst function 0 x three-key function is disable 1 0 generate three-key interrupt 1 1 hardware reset by three-key-reset [23] reserved - [22:19] k32r the #2 key row address the #2 means the row address and the column address is the highest of the specified 3-kyes. [18:16] k32c the #2 key column address [15] reserved - [14:11] k31r the #1 key row address the #1 means the row address and the column address is the 2nd of the specified 3-kyes. [10:8] k31c the #1 key column address [7] reserved - [6:3] k30r the #0 key row address the #0 means the row address and the column address is the lowest of the specified 3-kyes. [2:0] k30c the #0 key column address application note: due to hardware scan from {row[0], col[0]}, {row[0], col[1]}, ?, to {row[15], col[7]} the {k30r,k30c} should be filled the lo west address of the three-keys. for example, if {2,0} {4,6}, {1,3} keys are defined as three-keys. software s hould set {k30r, k30c} = {1, 3}, {k31r, k31c} = {2, 0} and {k32r, k32c} = {4, 6}. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 377 - revision a2 keypad interface low power mode c onfiguration register (kpilpconf) register address r/w description reset value kpilpcof 0xfff8_8008 w/r low power configuration register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 wake 15 14 13 12 11 10 9 8 lpwcen 7 6 5 4 3 2 1 0 reserved lpwr bits description [31:17] reserved - [16] wake lower power wakeup enable setting this bit enables low power wakeup 1 = wakeup enable 0 = not enable [15:8] lpwcen low power wakeup column enable specify columns for low power wakeup. for example, if user wants to use keys in row n and column 0, 2, 5 to wake up W90N745, then the lpwcen should be fill 8?b00100101. [7:4] reserved - [3:0] lpwr low power wakeup row address define the row address keys used to wakeup. for 16x8 or 8x8 (with 4:16 or 3:8 decoder) keypad key conf iguration, lpwr means ?hex? code but for 4x8 (without decoder), lpwr means ?binary? code. for example, if user wants to use a ll keys on row 3 of 16x8 keypad to wakeup W90N745, then 0x3 should be fill into this register but for 4x8 keypad it should be filled as 4?b1000. free datasheet http:///
W90N745cd/W90N745cdg - 378 - key pad interface status register (kpistatus) register address r/w description reset value kpistatus 0xfff8_800c r/o key pad status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved int 3 k r s t p d w a k e 3key 2key 1key 15 14 13 12 11 10 9 8 reserved key1r key1c 7 6 5 4 3 2 1 0 reserved key0r key0c bits description [31:22] reserved - [21] int key interrupt this bit indicates the key scan interrupt is active and that one or two keys have changed status. the interrupt also occur when the three specified keys are detected if e nrst bit in kpi3kfcon is cleared. it will be cleared by hardware aut omatically when software read kpistatus register. [20] 3krst 3-keys reset flag this bit is a record flag for software reference, it will be set after 3- keys reset occur. 1 = 3 keys reset 0 = not reset. this bit is cleared while it is read. [19] pdwake power down wakeup flag this flag indicates the chip is wakeup from power down by keypad 1 =wakeup up by keypad 0 = not wakeup [18] 3key specified three-key is detected. this flag indicates specified-thr ee-keys was detected. software can read this bit to know the key pad interrupt is 3 key or not. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 379 - revision a2 continued bits description [17] 2key double-key press this bit indicates that 2 keys have been detected. software can read {key1r, key1c} and {key0r, key0c} to know which two keys are pressed. [16] 1key single-key press this bit indicates that 1 key has been detected. software can read {key0r, key0c} to know which key is pressed. [15] reserved - [14:11] key1r key1 row address this value indicates key1 row address. the keypad controller scan keypad matrix from row 0, column0 ? 1 ? 2 ?. ? 7 and then row1 column 0 ? 1 ? 2 ? 7 so the lowest key address will be stored in {key0r, key0c}. this register stores the 2 nd address, if more than one key is pressed. [10:8] key1c key1 column address this value indicates key1 column address.. [7] reserved - [6:3] key0r key1 row address this value indicates key0 row address. this value indicates key0 row address. this value indicates key1 row address. the keypad controller scan keypad matrix from row 0, column0 ? 1 ? 2 ?. ? 7 and then row1 col 0 ? 1 ? 2 ? ? ? 7 still to row16 (or 8, or 4) column 0 ? 1 ? 2 ?.. ? 7 so the lowest key address will be stored in {key0r, key0c}. [2:0] key0c key1 column address this value indicates key0 row address. free datasheet http:///
W90N745cd/W90N745cdg - 380 - 6.18 ps2 host interface controller W90N745 ps2 host controller interface is an apb slav e consisted of ps2 pr otocol. it is used to connect to your ibm keyboard or other device thr ough ps2 interface. for example, the ibm keyboard will sends scan codes to the host controller, and t he scan codes will tell your keyboard bios what keys you have pressed or released. besides scan codes, commands can also be sent to the keyboard from host. the most common commands would be the setting/resetting of the status indicators (i.e. the num lock, caps lock & scroll lock leds). the ps2 interface implements a bi-directional prot ocol. the keyboard can send data to the host and the host can send data to the keyboard using tw o ps2 clock and ps2 data lines. both the ps2 clock and data lines are open collector bi-directional i/o lines. the host has the ultimate priority over direction. the keyboard is free to send dat a to the host when both the ps2 data and ps2 clock lines are high (idle). if the host takes the ps2 cl ock line low, the keyboard will buffer any data until the ps2 clock is released, ie goes high. the tr ansmission of data in the forward direction, ie keyboard to host is done with a frame of 11 bits. the first bit is a start bit (logic 0) followed by 8 data bits (lsb first), one parity bit (odd parity) and a stop bit (logic 1). each bit should be read on the falling edge of the clock. the keyboard will generat e the clock. the frequency of the clock signal typically ranges from 20 to 30 khz. the host to keyboard protocol is initiated by ta king the ps2 data line low. it is common to take the ps2 clock line low for more than 60us and then the kbd data line is taken low, while the kbd clock line is released. after that, the keyboard will start generating a clock signal on its ps2 clock line. after the first falling edge has been detected, host will load t he first data bit on the ps2 data line. this bit will be read into the keyboard on the next falling edge, a fter which host place the next bit of data. this process is repeated for the 8 data bits. it will follow an odd parity bit after the data byte. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 381 - revision a2 6.18.1 ps2 host controller interface register map register address r/w description reset value ps2cmd 0xfff8_9000 r/w ps2 host c ontroller command register 0x0000_0000 ps2sts 0xfff8_9004 r/w ps2 host cont roller status register 0x0000_0000 ps2scancode 0xfff8_9008 ro ps2 host controller rx scan code register 0x0000_0000 ps2ascii 0xfff8_900c ro ps2 host controller rx ascii code register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 382 - 6.18.2 register description ps2 host controller command register (ps2_cmd) register address r/w description reset value ps2cmd 0xfff8_9000 r/w command register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved trap_shift encmd 7 6 5 4 3 2 1 0 ps2cmd bits descriptions [31:10] reserved - [9] trap_shift trap shift key output to scan code register if the shift key scan code (0x12 0r 0x59) is received by host, software can indicate host whether to update to scan code register or not. no ascii or sc an codes will be reported for the shift keys if this bit is set. in this condition, host will only report the shift keys at the rx_shift_key bit of status register and no interrupt will occur for the shift ke ys. this is useful for those who wish to use the ascii data stream and don?t want to ?manually? filter out the shift key codes. this bit is clear by default. [8] encmd enable write ps2 host controller commands this bit enables the write function of host controller com m device. set this bit will start the write process of ps2cmd con t hardware will automatically clear this bit while write pr o finished. [7:0] ps2cmd ps2 host controller commands this command filed is sent by the host to the keyboard. t h common command would be the setting/resetting of th e indicators (i.e. the num lock, caps lock & scroll lock leds). free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 383 - revision a2 ps2 host controller status register (ps2_sts) register address r/w description reset value ps2sts 0xfff8_9004 r/w status register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved tx_err tx_irq reserved rx_irq bits descriptions [31:6] reserved - [5] tx_err this transmit error status bit indicates software that device doesn?t response ack after host wrote a command to it. this bit is valid when tx_irq is asserted. it will automatically reset after software starts next command writing process. this bit is read only. [4] tx_irq this transmit complete interrupt bit indicates software that the process of host controlle r writing command to device is finished. software needs to write one to this bit to clear this interrupt. [3:1] reserved [0] rx_irq this receive interrupt bit indicates software that host controller receives one byte dat a from device. this data is stored at ps2_scancode regist er. software needs to write one to this bit to clear this interrupt after reading receiving data in rx_scan_code register. note that the reception of the extend (0xe0) and release (0xf0) scan code will not cause an interrupt by host. the case of the shift key codes will be determined by the trap_shift bit of ps2_cmd register. free datasheet http:///
W90N745cd/W90N745cdg - 384 - ps2 host controller rx scan code register (ps2_scancode) register address r/w description reset value ps2scancode 0xffff_9008 r/w ps2 host rx scan code register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved rx_shift_key r x_release r x_extend 7 6 5 4 3 2 1 0 rx_scan_code bits descriptions [31:11] reserved - [10] rx_shift_key this receive shift key bit indicates that left or right shift key on the keyboard is hold. this bit is read only and will clear by host when the release shift key codes are received. [9] rx_release receive released byte when one key has been released, the keyboard will send f0 (hex) to inform host controller. this bit indicates software that host controller receives release byte (f0). this bit is read only and will update when host has received next data byte. [8] rx_extend receive extend byte a handful of the keys on key board are extended keys and thus require two more scan code. these keys are preceded by an e0 (hex). this bit indicates software that host controller receives extended byte (e0). this bit is read only and will update when host has received next data byte. [7:0] rx_scan_code ps2 host controller received data field this field stores the original data content transmitted from device. this filed is valid when rx_irq is asserted. note that host will not report ?extend? or ?r elease? scan code to this field and not generate interrupt if they are received by host, i.e. 0xe0 and 0xf0. the case of the shift key codes will be determined by the trap_shift bit of ps2_cmd register. free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 385 - revision a2 ps2 host controller rx ascii code register (ps2_ascii) register address r/w description reset value ps2ascii 0xfff8_900c r/w ps2 host rx ascii code register 0x0000_0000 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rx_ascii_code bits descriptions [31:8] reserved - [7:0] rx_ascii_code ps2 host controller received data filed this field stores the ascii data content transmitted from device. therefore, this part transla tes the scan code into an ascii value. it will be read as 0x2e when there is no ascii code mapped to the scan code stored in rx_scan_code register. this filed is valid when rx_irq is asserted. free datasheet http:///
W90N745cd/W90N745cdg - 386 - 7. electrical specifications 7.1 absolute maximum ratings ambient temper ature .................................?????............................. -40 c ~ +85 c storage temper ature ..................................................??.................... -40 c ~ +125 c voltage on any pin ...............................................................??.......... -0 .5v ~ 6v power supply voltage (core logi c) ..............................?...........???..?.. -0.5v ~ 1.92v power supply voltage (io buffe r) ...............................?...........???..?.. -0 .5v ~ 3.6v injection current (latch -up testing) ..............................................???.. 100ma crystal frequency ...............................................?...........???..???? 4m hz ~ 30mhz 7.2 dc specifications 7.2.1 digital dc characteristics (normal test conditions: vdd33/us bvdd = 3.3v+/- 0.3v, vdd18/dvdd18/avdd18 = 1.8v+/- 0.18v ta = -40 c ~ +85 c unless otherwise specified) symbol parameter condition min. max. unit vdd33/ usbvdd power supply 3.00 3.60 v vdd18/ dvdd18/ avdd18 power supply 1.62 1.98 v v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 5.5 v vt+ schmitt trigger positive-going threshold 1.47 1.5 v vt- schmitt trigger negative-going threshold 0.89 0.95 v v ol output low voltage depend on driving - 0.4 v v oh output high voltage depend on driving 2.4 - v free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 387 - revision a2 continued. symbol parameter condition min. max. unit i cc 1 1.8v supply current f cpu = 80mhz - 150 ma icc2 3.3v supply current f cpu = 80mhz - 60 ma icc rtc rtc 1.8v supply current f rtc = 32.768khz - 7 ua i ih input high current v in = 2.4 v -1 1 a i il input low current v in = 0.4 v -1 1 a i ihp input high current (pull-up) v in = 2.4 v -15 -10 a i ilp input low current (pull-up) v in = 0.4 v -55 -25 a i ihd input high current (pull-down) v in = 2.4 v 25 60 a i ild input low current (pull-down) v in = 0.4 v 5 10 a table 7.2.1 tsmc io dc characteristics parameter min. typ. max. v il input low voltage -0.3v 0.8v v i i h h input high voltage 2v 5.5v v t threshold point 1.46v 1.59v 1.75v v t+ schmitt trig low to high threshold point 1.47v 1.50v 1.50v v t- schmitt trig, high to low threshold point 0.90v 0.94v 0.96v i i input leakage current @v i = 3.3v or 0v +/- 10ua i oz tri-state output leakage current @vo =3.3v or 0v +/- 10ua r pu pull-up resister 44k ? 66k ? 110k ? r pd pull-down resister 25k ? 50k ? 110k ? v ol output low voltage @ iol (min) 0.4v v oh output high voltage @i oh (min) 2.4v free datasheet http:///
W90N745cd/W90N745cdg - 388 - continued. parameter min. typ. max. low level output current @v ol = 0.4v 4ma 4.9ma 7.4ma 9.8ma low level output current @v ol = 0.4v 8ma 9.7ma 14.9ma 19.5ma i ol low level output current @v ol = 0.4v 12ma 14.6ma 22.3ma 29.3ma high level output current @v oh = 2.4v 4ma 6.3ma 12.8ma 21.2ma high level output current @v oh = 2.4v 8ma 12.7ma 25.6ma 42.4ma i oh high level output current @v oh = 2.4v 12ma 19.0ma 38.4ma 63.6ma note: the values in this table are copied fr om tsmc 1p5m io library tpz937g_240b silicon report. this table is just for reference. more prec ision dc vaule should refer to alpha-test result. 7.2.2 usb transceiver dc characteristics symbol parameter conditions min. max. unit v di differential input sensitivity ? dp ? dm ? 0.2 v v cm differential common mode range includes v di range 0.8 2.5 v v se single ended receiver threshold 0.8 2.0 v v ol static output low voltage rl of 1.5 k to 3.6 v 0.3 v v oh static output high voltage rl of 15 k to vss 2.8 3.6 v v crs output signal crossover voltage 1.3 2.0 v z drv driver output resistanc e steady state drive 28 43 c in pin capacitance 20 pf free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 389 - revision a2 7.3 ac specifications 7.3.1 ebi/sdram interface ac characteristics t dh t dsu 1.5v output valid iutput valid 1.5v 1.5v 1.5v mclk mclk d[31:0] d[31:0] sdram input to w90p710 w90p710 write to sdram t do symbol parameter min. max. unit t dsu d [31:0] setup time 2 ns t dh d [31:0] hold time 2 ns t do d [31:0], a [24:0], nscs [1:0], sdqm [3:0], cke, nswe, nsras, nscas 2 7 ns free datasheet http:///
W90N745cd/W90N745cdg - 390 - 7.3.2 ebi/(rom/sram/external i/o) ac characteristics address valid r data write data vaild mclk t do necs[3:0] a[21:0] noe d[31:0] nwait nwbe[3:0] d[31:0] t necso t necso t addo t noeo t noeo t dsu t dh t nwah t nwbo t nwbo t nwasu symbol description min max unit t addo address output delay time 2 7 ns t ncso rom/sram/flash or external i/o chip select delay time 2 7 ns t noeo rom/sram or external i/o bank output enable delay 2 7 ns t nwbo rom/sram or external i/o bank write byte enable delay 2 7 ns t dh read data hold time 7 ns t dsu read data setup time 0 ns t do write data output delay time (sram or external i/o) 2 7 ns t nwasu external wait setup time 3 ns t nwah external wait hold time 1 ns free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 391 - revision a2 7.3.3 usb transceiver ac characteristics low speed: 75ns at c l = 50pf, 300ns at c l = 350pf full speed: 4 to 20ns at c l = 50pf differential data lines 1 0% rise time 90% fall time t f t r 1 0% 90% c l c l data signal rise and fall time usb transceiver ac characteristics symbol description conditions min max unit t r rise time cl = 50 pf 4 20 ns t f fall time cl = 50 pf 4 20 ns t rfm rise/fall time matching 90 110 % t drate full speed data rate average bit rate (12 mb/s 0.25%) 11.97 12.03 mbps 7.3.4 emc rmii ac characteristics the signal timing characteristics conforms to the guidelines specified in ieee std. 802.3. phy_refclk phy_txen phy_txd[1:0] t txo valid data t txh t freq t rxs t rxh phy_rxerr phy_rxd[1:0] phy_crsdv t duty valid data free datasheet http:///
W90N745cd/W90N745cdg - 392 - symbol description min typ max unit t freq rmii reference clock frequency 50 mhz t duty rmii clock duty 35% 50% 65% ns t txo transmit data output delay 5 - 15 ns t txh transmit data hold time 2 - - ns t rxs receive data setup time 4 - - ns t rxh receive data hold time 2 - - ns phy_mdc phy_mdio (write) t mdo valid data t mdh valid data t mds t mdh phy_mdio (read) symbol description min max unit t mdo mdio output delay time 0 15 ns t mdsu mdio setup time 5 ns t mdh mdio hold time 5 ns free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 393 - revision a2 7.3.5 ac97/i2s interface ac characteristics t isu t od t ihd t oh ac97_bclk ac97_datao ac97_sync ac97_datai t clk_period symbols description min typ. max unit t clk_period ac97 bit clock frequency -- 12.288 -- mhz t od ac97_datao and ac97_sync output delay from ac97_bclk rising edge -- -- 30 ns t oh ac97_datao and ac97_sync output hold time from ac97_bclk rising edge 5 -- -- ns t isu ac97_datai input setup time to ac97_bclk falling edge 10 -- -- ns t ihd ac97_datai input hold time from ac97_bclk falling edge 5 -- -- ns free datasheet http:///
W90N745cd/W90N745cdg - 394 - t dis t dih t doh t out_delay t bclk_period i 2 s_bclk i 2 s_datao i 2 s_rlclk i 2 s_datai symbols description min max unit t bclk_period iis bit clock frequency note:depend on codec spec. and register setting mhz t out_delay iis_datao and iis_rlclk output delay from iis_bclk falling edge -- 30 ns t doh iis_datao and iis_rlclk data output hold time from iis_bclk falling edge 0 -- ns t dis iis_datai input setup time to iis_bclk rising edge 10 -- ns t dih iis_datai input hold time from iis_bclk rising edge 100 -- ns free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 395 - revision a2 7.3.6 i 2 c interface ac characteristics t su:sto t su:dat2 t low t high t hd:dat t su:dat t hd:sta scl sda scl sda t su:sat symbol description min max unit t high i 2 c clock high time 1 - us t low i 2 c clock low time 1 - us t hd:sta start condition hold time 1 - us receive data setup time 0.1 - us t su:dat transmit data output delay - 0.5 us receive data hold time 1 - us t hd:dat transmit data hold time 0 0.9 us t su:dat2 sda setup time (before stop condition) 0.5 - us t su:sto stop condition setup time 1 - us t su:sta restart condition setup time 1.5 - us free datasheet http:///
W90N745cd/W90N745cdg - 396 - 7.3.7 usi interface ac characteristics t lag t od t od f usi t clkh t clkl t lead sfrm sclk ssptxd (tx_neg =1) ssptxd (tx_neg =0) f usi t lead t clkh t clkl t isu t isu t ih t ih t lag sfrm sclk ssprxd (rx_neg =1) ssprxd (rx_neg =0) free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 397 - revision a2 symbol description min max unit f usi usi clock frequency - 20 mhz t clkh usi clock high time 12.5 - ns t clkl usi clock low time - - ns t isu data input setup time - 14 ns t ih data input hold time 0 - ns t lead usi enable lead time 12.5 - ns t lag usi enable lag time 12.5 - ns t od usi output data valid time - 30 ns 7.3.8 ps2 interface ac characteristics ps2_clk ps2_data t1 t2 t3 t4 start bit bit 0 parity bit stop bit 1st clk 2nd clk 10th clk 11th clk timing for data received from the auxiliary device t9 t8 t7 1st clk 2nd clk 9th clk 10th clk 11th clk ps2_data ps2_clk parity bit timing for data send to the auxiliary device t5 bit 0 free datasheet http:///
W90N745cd/W90N745cdg - 398 - symbol description min. max. unit t1 time from data transition to falling edge of clk 5 25 us t2 time form rising edge of clk to data transition 5 t4-5 us t3 duration of clk inactive 30 50 us t4 duration of clock active 30 50 us t5 time to auxiliary device inhibit after clock 11 to ensure the auxiliary device does not start another transmission 0 50 us t7 duration of clk inactive 30 50 us t8 duration of clk active 30 50 us t9 time to fom inactive to active clk transition, used to time when the auxiliary device samples data 30 50 us free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 399 - revision a2 8. ordering information part number name package description W90N745cd lqfp128 128 leads, body 14 x 14 x 1.4 mm W90N745cdg lqfp128 128 leads, body 14 x 14 x 1.4 mm, lead free package free datasheet http:///
W90N745cd/W90N745cdg - 400 - 9. package specifications 128l lqfp (14x14x1.4 mm footprint 2.0mm) free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 401 - revision a2 10. appendix a: W90N745 registers mapping table r : read only, w : write only, r/w : both read and write, c : only value 0 can be written system manager control registers map register address r/w description reset value pdid 0xfff0_0000 r product identif ier register 0xx090.0 710 arbcon 0xfff0_0004 r/w arbitrati on control register 0x0000_0000 pllcon 0xfff0_0008 r/w pll control register 0x0000_2f01 clksel 0xfff0_000c r/w clock select register 0x1fff_3fx8 pllcon1 0xfff0_0010 r/w pll c ontrol register 2 0x0001_0000 i2sckcon 0xfff0_0014 r/w audio i 2 s clock control register 0x0000_0000 irqwakecon 0xfff0_0020 r/w irq wakeup control register 0x0000_0000 irqwakeflag 0xffff_0024 r/w irq wakeup flag register 0x0000_0000 pmcon 0xfff0_0028 r/w power manager control register 0x0000_0000 usbtxrcon 0xfff0_0030 r/w usb transce iver control register 0x0000_0000 external bus interface control registers map register address r/w description reset value ebicon 0xfff0_1000 r/w ebi c ontrol register 0x0001_0000 romcon 0xfff0_1004 r/w rom/flash control register 0x0000_0xfc sdconf0 0xfff0_1008 r/w sdram bank 0 configuration register 0x0000_0800 sdconf1 0xfff0_100c r/w sdram bank 1 configuration register 0x0000_0800 sdtime0 0xfff0_1010 r/w sdram bank 0 timing control register 0x0000_0000 sdtime1 0xfff0_1014 r/w sdram bank 1 timing control register 0x0000_0000 ext0con 0xfff0_1018 r/w external i/o 0 control register 0x0000_0000 ext1con 0xfff0_101c r/w external i/o 1 control register 0x0000_0000 ext2con 0xfff0_1020 r/w external i/o 2 control register 0x0000_0000 ext3con 0xfff0_1024 r/w external i/o 3 control register 0x0000_0000 ckskew 0xfff0_1f00 r/w clock skew contro l register (for testing) 0xxxxx_0038 free datasheet http:///
W90N745cd/W90N745cdg - 402 - cache control registers map register address r/w description reset value cahcnf 0xfff0_2000 r/w cache conf iguration register 0x0000_0000 cahcon 0xfff0_2004 r/w cache control register 0x0000_0000 cahadr 0xfff0_2008 r/w cache address register 0x0000_0000 emc registers map register address r/w description reset value c amcmr 0xfff0_3000 r/w cam command register 0x0000_0000 c amen 0xfff0_3004 r/w cam enable register 0x0000_0000 c am0m 0xfff0_3008 r/w cam0 most significant word register 0x0000_0000 c am0l 0xfff0_300c r/w cam0 least significant word register 0x0000_0000 c am1m 0xfff0_3010 r/w cam1 most significant word register 0x0000_0000 c am1l 0xfff0_3014 r/w cam1 least significant word register 0x0000_0000 c am2m 0xfff0_3018 r/w cam2 most significant word register 0x0000_0000 c am2l 0xfff0_301c r/w cam2 least significant word register 0x0000_0000 c am3m 0xfff0_3020 r/w cam3 most significant word register 0x0000_0000 c am3l 0xfff0_3024 r/w cam3 least significant word register 0x0000_0000 c am4m 0xfff0_3028 r/w cam4 most significant word register 0x0000_0000 c am4l 0xfff0_302c r/w cam4 least significant word register 0x0000_0000 c am5m 0xfff0_3030 r/w cam5 most significant word register 0x0000_0000 c am5l 0xfff0_3034 r/w cam5 least significant word register 0x0000_0000 c am6m 0xfff0_3038 r/w cam6 most significant word register 0x0000_0000 c am6l 0xfff0_303c r/w cam6 least significant word register 0x0000_0000 c am7m 0xfff0_3040 r/w cam7 most significant word register 0x0000_0000 c am7l 0xfff0_3044 r/w cam7 least significant word register 0x0000_0000 c am8m 0xfff0_3048 r/w cam8 most significant word register 0x0000_0000 c am8l 0xfff0_304c r/w cam8 least significant word register 0x0000_0000 c am9m 0xfff0_3050 r/w cam9 most significant word register 0x0000_0000 c am9l 0xfff0_3054 r/w cam9 least significant word register 0x0000_0000 c am10m 0xfff0_3058 r/w cam10 most significant word register 0x0000_0000 c am10l 0xfff0_305c r/w cam10 least significant word register 0x0000_0000 c am11m 0xfff0_3060 r/w cam11 most significant word register 0x0000_0000 c am11l 0xfff0_3064 r/w cam11 least significant word register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 403 - revision a2 emc registers map, continued register address r/w description reset value c am12m 0xfff0_3068 r/w cam12 most significant word register 0x0000_0000 c am12l 0xfff0_306c r/w cam12 least significant word register 0x0000_0000 c am13m 0xfff0_3070 r/w cam13 most significant word register 0x0000_0000 c am13l 0xfff0_3074 r/w cam13 least significant word register 0x0000_0000 c am14m 0xfff0_3078 r/w cam14 most significant word register 0x0000_0000 c am14l 0xfff0_307c r/w cam14 least significant word register 0x0000_0000 c am15m 0xfff0_3080 r/w cam15 most significant word register 0x0000_0000 c am15l 0xfff0_3084 r/w cam15 least significant word register 0x0000_0000 t xdlsa 0xfff0_3088 r/w t ransmit descriptor link list start address registe r 0xffff_fffc rxdlsa 0xfff0_308c r/w receive descriptor link list start addres s register 0xffff_fffc mcmdr 0xfff0_3090 r/w mac command register 0x0000_0000 miid 0xfff0_3094 r/w mii management data register 0x0000_0000 miida 0xfff0_3098 r/w mii management c ontrol and address register 0x0090_0000 fftcr 0xfff0_309c r/w fifo thre shold control register 0x0000_0101 t sdr 0xfff0_30a0 w t ransmit start demand register undefined rsdr 0xfff0_30a4 w receive star t demand register undefined dmarfc 0xfff0_30a8 r/w maximum rece ive frame control register 0x0000_0800 mien 0xfff0_30ac r/w mac inte rrupt enable register 0x0000_0000 mista 0xfff0_30b0 r/w mac interrupt status register 0x0000_0000 mgsta 0xfff0_30b4 r/w mac general status register 0x0000_0000 mpcnt 0xfff0_30b8 r/w missed packet count register 0x0000_7fff mrpc 0xfff0_30bc r mac receive pause count register 0x0000_0000 mrpcc 0xfff0_30c0 r mac receive pause current count register 0x0000_0000 mrepc 0xfff0_30c4 r mac remote pause count register 0x0000_0000 dmarfs 0xfff0_30c8 r/w dma receive frame status register 0x0000_0000 c txdsa 0xfff0_30cc r current transmit descriptor start addres s register 0x0000_0000 c txbsa 0xfff0_30d0 r current transmit buffer start address register 0x0000_0000 c rxds a 0xfff0_30d4 r current receive descriptor start addres s register 0x0000_0000 c rxbs a 0xfff0_30d8 r current receive buffe r start address register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 404 - emc registers map, continued register address r/w description reset value rxfsm 0xfff0_3200 r receive finite state machine register 0x0081_1101 t xfsm 0xfff0_3204 r t ransmit finite state machine register 0x0101_1101 fsm0 0xfff0_3208 r finite state machine register 0 0x0001_0101 fsm1 0xfff0_320c r finite state machine register 1 0x1100_0100 dcr 0xfff0_3210 r/w debug configuration register 0x0000_003f dmmir 0xfff0_3214 r debug mode mac information register 0x0000_0000 bistr 0xfff0_3300 r/w bist mode register 0x0000_0000 gdma registers map register address r/w description reset value gdma_ctl0 0xfff0_4000 r/w channel 0 control register 0x0000_0000 gdma_srcb0 0xfff0_4004 r/w channel 0 source base address register 0x0000_0000 gdma_dstb0 0xfff0_4008 r/w channel 0 destination base address register 0x0000_0000 gdma_tcnt0 0xfff0_400c r/w channel 0 transfer count register 0x0000_0000 gdma_csrc0 0xfff0_4010 r channel 0 current source address register 0x0000_0000 gdma_cdst0 0xfff0_4014 r channel 0 current destination address register 0x0000_0000 gdma_ctcnt 0 0xfff0_4018 r channel 0 current transfer count register 0x0000_0000 gdma_ctl1 0xfff0_4020 r/w channel 1 control register 0x0000_0000 gdma_srcb1 0xfff0_4024 r/w channel 1 source base address register 0x0000_0000 gdma_dstb1 0xfff0_4028 r/w channel 1 destination base address register 0x0000_0000 gdma_tcnt1 0xfff0_402c r/w channel 1 transfer count register 0x0000_0000 gdma_csrc1 0xfff0_4030 r channel 1 current source address register 0x0000_0000 gdma_cdst1 0xfff0_4034 r channel 1 current destination address register 0x0000_0000 gdma_ctcnt 1 0xfff0_4038 r channel 1 current transfer count register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 405 - revision a2 usb host controller registers map register address r/w description reset value openhci registers hcrevision 0xfff0_5000 r host controller revision register 0x0000_0010 hccontrol 0xfff0_5004 r/w host cont roller control register 0x0000_0000 hccommandstatus 0xfff0_5008 r/w host contro ller command status register 0x0000_0000 hcinterruptstatus 0xfff0_500c r/w host cont roller interrupt status register 0x0000_0000 hcinterruptenbale 0xfff0_5010 r/w host contro ller interrupt enable register 0x0000_0000 hcinterruptdisbale 0xfff0_5014 r/w host contro ller interrupt disable register 0x0000_0000 hchcca 0xfff0_5018 r/w host controller communication area register 0x0000_0000 hcperiodcurrented 0xfff0_501c r/w host cont roller period current ed register 0x0000_0000 hccontrolheaded 0xfff0_5020 r/w host contro ller control head ed register 0x0000_0000 hccontrolcurrented 0xfff0_5024 r/w host contro ller control current ed register 0x0000_0000 hcbulkheaded 0xfff0_5028 r/w host contro ller bulk head ed register 0x0000_0000 hcbulkcurrented 0xfff0_502c r/w host contro ller bulk current ed register 0x0000_0000 hcdoneheaded 0xfff0_5030 r/w host cont roller done head register 0x0000_0000 hcfminterval 0xfff0_5034 r/w host controlle r frame interval register 0x0000_2edf hcframeremaining 0xfff0_5038 r host contro ller frame remaining register 0x0000_0000 hcfmnumber 0xfff0_503c r host contro ller frame number register 0x0000_0000 hcperiodicstart 0xfff0_5040 r/w host cont roller periodic start register 0x0000_0000 hclsthreshold 0xfff0_5044 r/w host controlle r low speed threshold register 0x0000_0628 hcrhdescriptora 0xfff0_5048 r/w host controlle r root hub descriptor a register 0x0100_0002 hcrhdescriptorb 0xfff0_504c r/w host controlle r root hub descriptor b register 0x0000_0000 hcrhstatus 0xfff0_5050 r/w host controlle r root hub status register 0x0000_0000 hcrhportstatus [1] 0xfff0_5054 r/w host cont roller root hub port status [1] 0x0000_0000 hcrhportstatus [2] 0xfff0_5058 r/w host cont roller root hub port status [2] 0x0000_0000 usb configuration registers testmodeenable 0xfff0_5200 r/w usb test mode enable register 0x0xxx_xxxx operationalmodeenable 0xfff 0_5204 r/w usb operational m ode enable register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 406 - usb device register map register offset r/w description reset value usb_ctl 0xfff0_6000 r/w usb control register 0x0000_000 0 vcmd 0xfff0_6004 r/w usb class or vendor command register 0x0000_000 0 usb_ie 0xfff0_6008 r/w usb interrupt enable register 0x0000_000 0 usb_is 0xfff0_600 c r usb interrupt status register 0x0000_000 0 usb_ic 0xfff0_6010 r/w usb interr upt status clear register 0x0000_000 0 usb_ifstr 0xfff0_6014 r/w usb interface and string register 0x0000_000 0 usb_odata0 0xfff0_6018 r usb contro l transfer-out port 0 register 0x0000_000 0 usb_odata1 0xfff0_601 c r usb control transfer-out port 1 register 0x0000_000 0 usb_odata2 0xfff0_6020 r usb contro l transfer-out port 2 register 0x0000_000 0 usb_odata3 0xfff0_6024 r usb contro l transfer-out port 3 register 0x0000_000 0 usb_idata0 0xfff0_6028 r/w usb tr ansfer-in data port0 register 0x0000_000 0 usb_idata1 0xfff0_602 c r/w usb control transfer-in data port 1 0x0000_000 0 usb_idata2 0xfff0_6030 r/w usb control transfer-in data port 2 0x0000_000 0 usb_idata3 0xfff0_6034 r/w usb control transfer-in data port 3 0x0000_000 0 usb_sie 0xfff0_6038 r usb sie status register 0x0000_000 0 usb_eng 0xfff0_603 c r/w usb engine register 0x0000_000 0 usb_ctls 0xfff0_6040 r usb control transfer status register 0x0000_000 0 usb_confd 0xfff0_6044 r/w usb configured value register 0x0000_000 0 epa_info 0xfff0_6048 r/w usb endpoint a information register 0x0000_000 0 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 407 - revision a2 epa_ctl 0xfff0_604 c r/w usb endpoint a control register 0x0000_000 0 epa_ie 0xfff0_6050 r/w usb endpoint a interrupt enable register 0x0000_000 0 epa_ic 0xfff0_6054 w usb endpoint a interrupt clear register 0x0000_000 0 epa_is 0xfff0_6058 r usb endpoint a interrupt status register 0x0000_000 0 epa_addr 0xfff0_605 c r/w usb endpoint a address register 0x0000_000 0 epa_lenth 0xfff0_6060 r/w usb endpoint a transfer length register 0x0000_000 0 epb_info 0xfff0_6064 r/w usb endpoint b information register 0x0000_000 0 epb_ctl 0xfff0_6068 r/w usb endpoint b control register 0x0000_000 0 epb_ie 0xfff0_606 c r/w usb endpoint b interrupt enable register 0x0000_000 0 epb_ic 0xfff0_6070 w usb endpoint b interrupt clear register 0x0000_000 0 epb_is 0xfff0_6074 r usb endpoint b interrupt status register 0x0000_000 0 epb_addr 0xfff0_6078 r/w usb endpoint b address register 0x0000_000 0 free datasheet http:///
W90N745cd/W90N745cdg - 408 - usb device register map, continued register offset r/w description reset value epb_lenth 0xfff0_607c r/w usb endpoint b transfer length register 0x0000_0000 epc_info 0xfff0_6080 r/w usb endpoint c information register 0x0000_0000 epc_ctl 0xfff0_6084 r/w usb endpoint c control register 0x0000_0000 epc_ie 0xfff0_6 088 r/w usb endpoint c interrupt enable register 0x0000_0000 epc_ic 0xfff0_608c w usb endpoint c interrupt clear register 0x0000_0000 epc_is 0xfff0_6090 r usb endpoint c in terrupt status register 0x0000_0000 epc_addr 0xfff0_6094 r/w usb endpoint c address register 0x0000_0000 epc_lenth 0xfff0_6098 r/w usb endpoint c transfer length register 0x0000_0000 epa_xfer 0xfff0_609c r/w usb endpoint a remain transfer length register 0x0000_0000 epa_pkt 0xfff0_60a0 r/w usb endpoint a remain packet length register 0x0000_0000 epb_xfer 0xfff0_60a4 r/w usb endpoint b remain transfer length register 0x0000_0000 epb_pkt 0xfff0_60a8 r/w usb endpoint b remain packet length register 0x0000_0000 epc_xfer 0xfff0_60ac r/w usb endpoint c remain transfer length register 0x0000_0000 epc_pkt 0xfff0_60b0 r/w usb endpoint c remain packet length register 0x0000_0000 audio control register map register address r/w description reset value actl_con 0xfff0_9000 r/w audio cont roller control register 0x0000_0000 actl_reset 0xfff0_9004 r/w sub block reset control register 0x0000_0000 actl_rdstb 0xfff0_9008 r/w dma destination base address register for record 0x0000_0000 actl_rdst_length 0xfff0_900c r/w dma destination length register for record 0x0000_0000 actl_rdstc 0xfff0_9010 r dma destination current address register for record 0x0000_0000 actl_rsr 0xfff0_9014 r/w recor d status register 0x0000_0000 actl_pdstb 0xfff0_9018 r/w dma destination base address register for play 0x0000_0000 actl_pdst_length 0xfff0_901c r/w dma destination length register for play 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 409 - revision a2 audio control register map, continued register address r/w description reset value actl_pdstc 0xfff0_9020 r dma destination current address register for play 0x0000_0000 actl_psr 0xfff0_9024 r/w play status register 0x0000_0004 actl_i2scon 0xfff0_9028 r/w i2 s control register 0x0000_0000 actl_accon 0xfff0_902c r/w ac- link control register 0x0000_0000 actl_acos0 0xfff0_9030 r/w ac-link out slot 0 0x0000_0000 actl_acos1 0xfff0_9034 r/w ac-link out slot 1 0x0000_0080 actl_acos2 0xfff0_9038 r/w ac-link out slot 2 0x0000_0000 actl_acis0 0xfff0_903c r ac-link in slot 0 0x0000_0000 actl_acis1 0xfff0_9040 r ac-link in slot 1 0x0000_0000 actl_acis2 0xfff0_9044 r ac-link in slot 2 0x0000_0000 cache controller test registers map register address r/w description reset value ctest0 0xfff6_0000 r/w cache test register 0 0x0000_0000 ctest1 0xfff6_0004 r cache test register 1 0x0000_0000 uart0 control registers map register address r/w description reset value uart0_rbr 0xfff8_0000 r receive buffer register (dlab = 0) undefined uart0_thr 0xfff8_0000 w transmit holdi ng register (dlab = 0) undefined uart0_ier 0xfff8_0004 r/w interrupt enable register (dlab = 0) 0x0000_0000 uart0_dll 0xfff8_0000 r/w divisor latch register (ls) (dlab = 1) 0x0000_0000 uart0_dlm 0xfff8_0004 r/w divisor latch register (ms) (dlab = 1) 0x0000_0000 uart0_iir 0xfff8_0008 r interrupt identification register 0x8181_8181 uart0_fcr 0xfff8_0008 w fifo c ontrol register undefined uart0_lcr 0xfff8_000c r/w li ne control register 0x0000_0000 uart0_lsr 0xfff8_0014 r line status register 0x6060_6060 uart0_tor 0xfff8_001c r time out register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 410 - high speed uart1 control registers map register address r/w description reset value uart1_rbr 0xfff8_0100 r receive buffer register (dlab = 0) undefined uart1_thr 0xfff8_0100 w transmit holdi ng register (dlab = 0) undefined uart1_ier 0xfff8_0104 r/w interrupt e nable register (dlab = 0) 0x0000_0000 uart1_dll 0xfff8_0100 r/w divisor latch register (ls) (dlab = 1) 0x0000_0000 uart1_dlm 0xfff8_0104 r/w divisor latch register (ms) (dlab = 1) 0x0000_0000 uart1_iir 0xfff8_0108 r interrupt identification register 0x8181_8181 uart1_fcr 0xfff8_0108 w fifo c ontrol register undefined uart1_lcr 0xfff8_010c r/w line control register 0x0000_0000 uart1_mcr 0xfff8_0110 r/w modem control register 0x0000_0000 uart1_lsr 0xfff8_0114 r line st atus register 0x6060.6060 uart1_msr 0xfff8_0118 r mode m status register 0x0000_0000 uart1_tor 0xfff8_011c r time out register 0x0000_0000 uart1_ubcr 0xfff8_0120 r/w uart1 bl uetooth control register 0x0000_0000 uart2 control register map register address r/w description reset value uart2_rbr 0xfff8_0200 r receive buffer register (dlab = 0) undefined uart2_thr 0xfff8_0200 w transmit holdi ng register (dlab = 0) undefined uart2_ier 0xfff8_0204 r/w interrupt enable register (dlab = 0) 0x0000_0000 uart2_dll 0xfff8_0200 r/w divisor latch register (ls) (dlab = 1) 0x0000_0000 uart2_dlm 0xfff8_0204 r/w divisor latch register (ms) (dlab = 1) 0x0000_0000 uart2_iir 0xfff8_0208 r interrupt identification register 0x8181_8181 uart2_fcr 0xfff8_0208 w fifo c ontrol register undefined uart2_lcr 0xfff8_020c r/w li ne control register 0x0000_0000 uart2_mcr 0xfff8_0210 r/w modem control register 0x0000_0000 uart2_lsr 0xfff8_0214 r line status register 0x6060_6060 uart2_msr 0xfff8_0218 r mode m status register 0x0000_0000 uart2_tor 0xfff8_021c r time out register 0x0000_0000 uart2_ircr 0xfff8_0220 r/w irda control register 0x0000_0040 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 411 - revision a2 uart3 control register map register address r/w description reset value uart3_rbr 0xfff8_0300 r receive buffer register (dlab = 0) undefined uart3_thr 0xfff8_0300 w transmit holdi ng register (dlab = 0) undefined uart3_ier 0xfff8_0304 r/w interrupt enable register (dlab = 0) 0x0000_0000 uart3_dll 0xfff8_0300 r/w divisor latch register (ls) (dlab = 1) 0x0000_0000 uart3_dlm 0xfff8_0304 r/w divisor latch register (ms) (dlab = 1) 0x0000_0000 uart3_iir 0xfff8_0308 r interrupt identification register 0x8181_8181 uart3_fcr 0xfff8_0308 w fifo c ontrol register undefined uart3_lcr 0xfff8_030c r/w li ne control register 0x0000_0000 uart3_mcr 0xfff8_0310 r/w modem control register 0x0000_0000 uart3_lsr 0xfff8_0314 r line status register 0x6060_6060 uart3_msr 0xfff8_0318 r mode m status register 0x0000_0000 uart3_tor 0xfff8_031c r time out register 0x0000_0000 timer control registers map register address r/w description reset value tcr0 0xfff8_1000 r/w timer control register 0 0x0000_0005 tcr1 0xfff8_1004 r/w timer control register 1 0x0000_0005 ticr0 0xfff8_1008 r/w timer initia l control register 0 0x0000_00ff ticr1 0xfff8_100c r/w timer init ial control register 1 0x0000_00ff tdr0 0xfff8_1010 r timer data register 0 0x0000_0000 tdr1 0xfff8_1014 r timer data register 1 0x0000_0000 tisr 0xfff8_1018 r/c timer inte rrupt status register 0x0000_0000 wtcr 0xfff8_101c r/w watchdog t imer control register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 412 - aic control registers map register address r/w description reset value aic_scr1 0xfff8_2004 r/w source control register 1 0x0000_0047 aic_scr2 0xfff8_2008 r/w source control register 2 0x0000_0047 aic_scr3 0xfff8_200c r/w sour ce control register 3 0x0000_0047 aic_scr4 0xfff8_2010 r/w source control register 4 0x0000_0047 aic_scr5 0xfff8_2014 r/w source control register 5 0x0000_0047 aic_scr6 0xfff8_2018 r/w source control register 6 0x0000_0047 aic_scr7 0xfff8_201c r/w sour ce control register 7 0x0000_0047 aic_scr8 0xfff8_2020 r/w source control register 8 0x0000_0047 aic_scr9 0xfff8_2024 r/w source control register 9 0x0000_0047 aic_scr10 0xfff8_2028 r/w source control register 10 0x0000_0047 aic_scr11 0xfff8_202c r/w sour ce control register 11 0x0000_0047 aic_scr12 0xfff8_2030 r/w source control register 12 0x0000_0047 aic_scr13 0xfff8_2034 r/w source control register 13 0x0000_0047 aic_scr14 0xfff8_2038 r/w source control register 14 0x0000_0047 aic_scr15 0xfff8_203c r/w sour ce control register 15 0x0000_0047 aic_scr16 0xfff8_2040 r/w source control register 16 0x0000_0000 aic_scr17 0xfff8_2044 r/w source control register 17 0x0000_0000 aic_scr18 0xfff8_2048 r/w source control register 18 0x0000_0000 aic_scr19 0xfff8_204c r/w source control register 19 0x0000_0047 aic_scr20 0xfff8_2050 r/w source control register 20 0x0000_0047 aic_scr21 0xfff8_2054 r/w source control register 21 0x0000_0047 aic_scr22 0xfff8_2058 r/w source control register 22 0x0000_0047 aic_scr23 0xfff8_205c r/w source control register 23 0x0000_0047 aic_scr24 0xfff8_2060 r/w source control register 24 0x0000_0047 aic_scr25 0xfff8_2064 r/w source control register 25 0x0000_0047 aic_scr26 0xfff8_2068 r/w source control register 26 0x0000_0047 aic_scr27 0xfff8_206c r/w source control register 27 0x0000_0047 aic_scr28 0xfff8_2070 r/w source control register 28 0x0000_0047 aic_scr29 0xfff8_2074 r/w source control register 29 0x0000_0047 aic_scr30 0xfff8_2078 r/w source control register 30 0x0000_0047 aic_scr31 0xfff8_207c r/w source control register 31 0x0000_0047 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 413 - revision a2 aic control registers map, continued register address r/w description reset value aic_irsr 0xfff8_2100 r interrupt raw status register 0x0000_0000 aic_iasr 0xfff8_2104 r interrupt active status register 0x0000_0000 aic_isr 0xfff8_2108 r interrupt status register 0x0000_0000 aic_iper 0xfff8_210c r interrupt priority encoding register 0x0000_0000 aic_isnr 0xfff8_2110 r interrupt s ource number register 0x0000_0000 aic_imr 0xfff8_2114 r interrupt mask register 0x0000_0000 aic_oisr 0xfff8_2118 r output in terrupt status register 0x0000_0000 aic_mecr 0xfff8_2120 w mask enabl e command register undefined aic_mdcr 0xfff8_2124 w mask disabl e command register undefined aic_sscr 0xfff8_2128 w source set command register undefined aic_sccr 0xfff8_212c w source cl ear command register undefined aic_eoscr 0xfff8_2130 w end of service command register undefined aic_test 0xfff8_2200 w ice/debug mode register u ndefined gpio control register map register address r/w description reset value gpio_cfg0 0xfff8_3000 r/w gpio port0 configuration register 0x0000_0000 gpio_dir0 0xfff8_3004 r/w gpio port0 di rection control register 0x0000_0000 gpio_dataout0 0xfff8_3008 r/w gpio port 0 data output register 0x0000_0000 gpio_datain0 0xfff8_300c r gpio po rt0 data input register 0xxxxx_xxxx gpio_cfg1 0xfff8_3010 r/w gpio port1 configuration register 0x0000_0000 gpio_dir1 0xfff8_3014 r/w gpio port1 di rection control register 0x0000_0000 gpio_dataout1 0xfff8_3018 r/w gpio por t1 data output register 0x0000_0000 gpio_datain1 0xfff8_301c r gpio port1 data input register 0xxxxx_xxxx gpio_cfg2 0xfff8_3020 r/w gpio port2 configuration register 0x0000_0000 gpio_dir2 0xfff8_3024 r/w gpio port2 di rection control register 0x0000_0000 gpio_dataout2 0xfff8_3028 r/w gpio port 2 data output register 0x0000_0000 gpio_datain2 0xfff8_302c r gpio po rt2 data input register 0xxxxx_xxxx gpio_cfg4 0xfff8_3040 r/w gpio port4 configuration register 0x0015_5555 gpio_dir4 0xfff8_3044 r/w gpio port4 di rection control register 0x0000_0000 gpio_dataout4 0xfff8_3048 r/w gpio port 4 data output register 0x0000_0000 gpio_datain4 0xfff8_304c r gpio po rt4 data input register 0xxxxx_xxxx free datasheet http:///
W90N745cd/W90N745cdg - 414 - gpio control register map, continued register address r/w description reset value gpio_cfg5 0xfff8_3050 r/w gpio port5 configuration register 0x0000_0000 gpio_dir5 0xfff8_3054 r/w gpio port5 di rection control register 0x0000_0000 gpio_dataout5 0xfff8_3058 r/w gpio port 5 data output register 0x0000_0000 gpio_datain5 0xfff8_305c r gpio po rt5 data input register 0xxxxx_xxxx gpio_dbncecon 0xfff8_3070 r/w gpio input debounce control register 0x0000_0000 gpio_xicfg 0xfff8_3074 r/w extend interr upt configure register 0xxxxx_xxx0 gpio_xistatus 0xfff8_3078 r/w extend inte rrupt status register 0xxxxx_xxx0 i 2 c register map register address r/w description reset value i 2 c interface 0 i 2 c_csr0 0xfff8_6000 r/w i 2 c0 control and status register 0x0000_0000 i 2 c_divider0 0xfff8_6004 r/w i 2 c0 clock prescale register 0x0000_0000 i 2 c_cmdr0 0xfff8_6008 r/w i 2 c0 command register 0x0000_0000 i 2 c_swr0 0xfff8_600c r/w i 2 c0 software mode control register 0x0000_003f i 2 c_rxr0 0xfff8_6010 r i 2 c0 data receive register 0x0000_0000 i 2 c_txr0 0xfff8_6014 r/w i 2 c0 data transmit register 0x0000_0000 i 2 c interface 1 i 2 c_csr1 0xfff8_6000 r/w i 2 c1 control and status register 0x0000_0000 i 2 c_divider1 0xfff8_6004 r/w i 2 c1 clock prescale register 0x0000_0000 i 2 c_cmdr1 0xfff8_6008 r/w i 2 c1 command register 0x0000_0000 i 2 c_swr1 0xfff8_600c r/w i 2 c1 software mode control register 0x0000_003f i 2 c_rxr1 0xfff8_6010 r i 2 c1 data receive register 0x0000_0000 i 2 c_txr1 0xfff8_6014 r/w i 2 c1 data transmit register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 415 - revision a2 usi register map register address r/w description reset value usi_cntrl 0xfff8_6200 r/w contro l and status register 0x0000_0004 usi_divider 0xfff8_6204 r/w clo ck divider register 0x0000_0000 usi_ssr 0xfff8_6208 r/w slave select register 0x0000_0000 reserved 0xfff8_620c n/a reserved n/a usi_rx0 0xfff8_6210 r data receive register 0 0x0000_0000 usi_rx1 0xfff8_6214 r data receive register 1 0x0000_0000 usi_rx2 0xfff8_6218 r data receive register 2 0x0000_0000 usi_rx3 0xfff8_621c r data receive register 3 0x0000_0000 usi_tx0 0xfff8_6210 w data transmit register 0 0x0000_0000 usi_tx1 0xfff8_6214 w data transmit register 1 0x0000_0000 usi_tx2 0xfff8_6218 w data transmit register 2 0x0000_0000 usi_tx3 0xfff8_621c w data transmit register 3 0x0000_0000 pwm control registers map register address r/w description reset value pwm_ppr 0xfff8_7000 r/w pwm prescaler register 0x0000_0000 pwm_csr 0xfff8_7004 r/w pwm clo ck select register 0x0000_0000 pwm_pcr 0xfff8_7008 r/w pwm control register 0x0000_0000 pwm_cnr0 0xfff8_700c r/w pwm counter register 0 0x0000_0000 pwm_cmr0 0xfff8_7010 r/w pwm comparator register 0 0x0000_0000 pwm_pdr0 0xfff8_7014 r pwm data register 0 0x0000_0000 pwm_cnr1 0xfff8_7018 r/w pwm counter register 1 0x0000_0000 pwm_cmr1 0xfff8_701c r/w pwm comparator register 1 0x0000_0000 pwm_pdr1 0xfff8_7020 r pwm data register 1 0x0000_0000 pwm_cnr2 0xfff8_7024 r/w pwm counter register 2 0x0000_0000 pwm_cmr2 0xfff8_7028 r/w pwm comparator 2 0x0000_0000 pwm_pdr2 0xfff8_702c r pwm data register 2 0x0000_0000 pwm_cnr3 0xfff8_7030 r/w pwm counter register 3 0x0000_0000 pwm_cmr3 0xfff8_7034 r/w pwm comparator register 3 0x0000_0000 pwm_pdr3 0xfff8_7038 r pwm data register 3 0x0000_0000 pwm_pier 0xfff8_703c r/w pwm in terrupt enable register 0x0000_0000 pwm_piir 0xfff8_7040 r/c pwm interr upt indication register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg - 416 - kpi control register map register address r/w description reset value kpiconf 0xfff8_8000 r/w keypad controlle r configuration register 0x0000_0000 kpi3kconf 0xfff8_8004 r/w keypad controller 3-keys configuration register 0x0000_0000 kpilpconf 0xfff8_8008 r/w keypad cont roller low power configuration register 0x0000_0000 kpistatus 0xfff8_800c r/o keypad c ontroller status register 0x0000_0000 ps2 control register map register address r/w/c description reset value ps2cmd 0xfff8_9000 r/w ps2 host c ontroller command register 0x0000_0000 ps2sts 0xfff8_9004 r/w ps2 host cont roller status register 0x0000_0000 ps2scancode 0xfff8_9008 ro ps2 host controller rx scan code register 0x0000_0000 ps2ascii 0xfff8_900c ro ps2 host controller rx ascii code register 0x0000_0000 free datasheet http:///
W90N745cd/W90N745cdg publication release date: september 22, 2006 - 417 - revision a2 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. free datasheet http:///

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